RS08KA2 PROMO Freescale Semiconductor, RS08KA2 PROMO Datasheet - Page 14

• Manufacturer Part Number: RS08KA2 PROMO
• Description: DEMO KIT, SILICON BUNDLE, RS08KA2
• Manufacturer: Freescale Semiconductor

Specifications of RS08KA2 PROMO

• Kit Contents: DEMO9RS08KA2 Board, USB Cable, Quick Start Guide, User Manual, Packing List
• Svhc: No SVHC (15-Dec-2010)
• Development Tool Type: Demonstration Kit
• Kit Features: RS08KA2 Microcontroller,
• Silicon Manufacturer: Freescale
• Core Architecture: RS08
• Core Sub-architecture: RS08
• Silicon Core Number: MC9RS08
• Silicon Family Name: RS08KA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Introduction to RS08
1.2.2
Using register X located in $000F and register D[X] located in $000E, most HC08/S08 zero offset index
addressing instructions and accumulator instructions can be emulated. This index addressing can be
performed on virtually all direct addressing mode instructions.
instructions supported in RS08 platform and their operations.
14
Add with Carry
Add without Carry
Logical AND
Clear Bit n in Memory
Branch if Bit n in Memory
Clear
Branch if Bit n in Memory Set
Set Bit n in Memory
Compare and Branch if Equal
Load Accumulator from Memory
Store Accumulator in Memory
Clear
Add without Carry
Subtract
Increment
Decrement
Operation
Pseudo Instructions
Description
Instruction translation is done during time of compilation by the assembler,
and is transparent to the user.
Table 1-3. RS08 Tiny and Short Addressing Mode Instructions
ADC ,X
ADC X
ADD ,X
ADD X
AND ,X
AND X
BCLR n,D[X]
BCLR n,X
BRCLR n,D[X],rel
BRCLR n,X,rel
BRSET n,D[X],rel
BRSET n,X,rel
BSET n,D[X]
BSET n,X
CBEQ ,X,rel
CBEQ X rel
Instruction
Pseudo
Table 1-4. Pseudo Instructions in RS08 Platform
Tiny/Short Instruction
Getting Started with RS08, Rev. 1
ADC $0E
ADC $0F
ADD <$0E
ADD <$0F
AND $0E
AND $0F
BCLR n, $0E
BCLR n, $0F
BRCLR n, $0E, rel
BRCLR n, $0F, rel
BRSET n, $0E, rel
BRSET n, $0F, rel
BSET n, $0E
BSET n, $0F
CBEQ $0E, rel
CBEQ $0F, rel
ADD opr4
SUB opr4
DEC opr4
LDA opr5
CLR opr5
STA opr5
INC opr4
Emulation
NOTE
PC ← (PC) + $0003 + rel ? (A) – (M) = $00
PC ← (PC) + $0003 + rel ? (A) – (X) = $00
Addressable Space
PC ← (PC) + $0003 + rel ? (Mn) = 0
PC ← (PC) + $0003 + rel ? (Mn) = 1
PC ← (PC) + $0003 + rel ? (Xn) = 0
PC ← (PC) + $0003 + rel ? (Xn) = 1
$0000 to $001F
$0000 to $001F
$0000 to $001F
$0000 to $000F
$0000 to $000F
$0000 to $000F
$0000 to $000F
Table 1-4
A ← (A) + (M) + (C)
A ← (A) + (X) + (C)
Description
A ← (A) + (M)
A ← (A) & (M)
A ← (A) + (X)
A ← (A) & (X)
Mn ← 0
Mn ← 1
Xn ← 0
Xn ← 1
summarizes all of the pseudo
Coding Example
Freescale Semiconductor
ADD <$0F
ADD <$00
SUB <$0F
DEC <$0F
DEC <$00
LDA <$1F
CLR <$1F
CLR <$00
SUB <$00
LDA <$00
STA <$1F
STA <$00
INC <$0F
INC <$00
Bytes Cycles
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2
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5
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