CME12BC32 AXIOM, CME12BC32 Datasheet - Page 13

• Manufacturer Part Number: CME12BC32
• Description: Microprocessor Development Tool
• Manufacturer: AXIOM

Specifications of CME12BC32

• Silicon Manufacturer: Freescale
• Core Architecture: HC12
• Kit Contents: Development Board With 64K SRAM And 32K Flash
• Silicon Family Name: HC12
• Silicon Core Number: 68HC12BC32, 68HC12B32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pins 1, 4, and 6 are connected for default handshake standards.
Pins 7 and 8 are connected for default handshake standards.
Handshake pins can be easily isolated and connected to I/O ports if necessary.
J2
BUS_PORT
The BUS_PORT supports off-board memory devices as follows:
GND
/ WE 25 26 CS0
GND 39 40 / RESET
1 T2IN
2 R2OUT
3 R2IN
4 T2OUT
RXD0 3 7
/ OE 15 16 A4
/RW 35 36 CS6
TXD0 2 6
CS1 27 28 CS2
CS3 29 30 CS4
CS5 31 32 IRQ
D10
A10 13 14 A3
A11 17 18 A5
A12 23 24 A13
+5V 33 34 /P-SEL
GND 5 9
D9
D8
A0
A1 11 12 A2
A9 19 20 A6
A8 21 22 A7
E 37 38 CS7
1 2
3 4
5 6
7 8
9 10 D15
1
4 8
The J2 connector (near COM1) contains spare RS232 translator inputs
and outputs. It can be used for implementing hardware handshaking on
COM1 if necessary.
D11
D12
D13
D14
The COM-1 port has a Female DB9 connector that interfaces to
the HC12 internal SCI0 serial port. It uses a simple 2 wire
asynchronous serial interface.
D8 - D15 High Byte Data Bus in Wide Expanded Mode and
Peripheral 8 bit data bus. Port A in Single Chip Mode.
A0 – A15 Memory Addresses 0 to 15.
/OE Memory Output Enable signal, Active Low. Valid with ECLK
and R/W high.
CS0 – CS7 Peripheral chip selects, 16 bytes each located at
$200 - $27F hex, 8 bit access (narrow bus).
/WE Memory Write Enable signal, Active Low. Valid with ECLK
high and R/W low.
IRQ HC12 IRQ (PE1) Interrupt Input.
/RW HC12 Read/Write (PE2) control signal.
E HC12 ECLK (PE4) bus clock signal. Stretch should be enabled
in software.
/P-SEL Selects Peripheral area, register following space, 8 bits
wide.
/RESET HC12 active low RESET signal.
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