CDB6420 Cirrus Logic Inc, CDB6420 Datasheet - Page 28

• Manufacturer Part Number: CDB6420
• Description: Development Kit
• Manufacturer: Cirrus Logic Inc

Specifications of CDB6420

• Silicon Manufacturer: Cirrus Logic
• Application Sub Type: Speakerphone
• Kit Application Type: Audio / Video / TV
• Silicon Core Number: CS6420
• Kit Contents: Board
• Kit Features: Analog And Digital Patch Area
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The three pins that comprise the Microcontroller
Interface are STROBE, DATA, and DRDY.
STROBE must not exceed the system clock of the
CS6420 in speed. Also, four extra clocks are re-
quired after DRDY is brought high in order to latch
the data into the CS6420, as is shown in Figure 5.
Grounding Considerations
Proper grounding of the CS6420 is necessary for
optimal performance from this mixed-signal de-
vice. The CS6420 should be considered an analog
device for grounding purposes.
The digital sections of the CS6420 are synchro-
nized with its ADCs and DACs to minimize the ef-
fects of digital noise coupling. However, for
external digital devices that are asynchronous with
respect to the CS6420, precautions should be taken
to minimize the chances of digital noise coupling
into the CS6420.
A design with the CS6420 should have a separate
ground plane for any digital devices. For example,
a system microcontroller should be on a digital
ground plane with its control lines leading to the
CS6420 in the shortest reasonable distance. The
CS6420 itself should lie completely on the analog
ground plane.
Layout Considerations
The physical layout of the traces and components
around the CS6420 will also strongly affect the per-
formance of the device. Special attention must be
paid to decoupling capacitors, the crystal oscillator,
and the input anti-aliasing filters.
The decoupling capacitors for the power supplies
of the CS6420 should be placed as close as possible
to the power pins for best performance. There are
two capacitors per pin: the 0.1 F capacitor needs
to be closest to the pin to decouple the high fre-
quency components, and the larger cap can be far-
ther away. The MB pin is the most critical as it
connects directly to the on-chip voltage reference.
28
AVDD and DVDD are secondary to MB with re-
spect to priority.
The crystal oscillator should be placed as close as
possible to reduce the distance that the high fre-
quency signals must travel. If the crystal is placed
too far away, the trace inductance may cause prob-
lems with oscillator startup.
The next concern with placement is the input anti-
aliasing filters for the ADC inputs. NI has an RC
low-pass network with a corner frequency of 8
kHz. The capacitor of this low-pass network should
be placed very close to the pin so that there is very
little exposed trace to pick up noise. If the on-chip
microphone amplifier is used, the 0.022 F capac-
itor on APO will provide the appropriate cutoff fre-
quency, and so should be placed close to the APO
pin. If the on-board preamplifier is not used, APO
will have the same RC network as NI, and should
be treated similarly.
The connections from the controller to the Micro-
controller Interface should be short straight traces,
if possible. The traces should not run very close to
any digital clocks to avoid cross coupling.
System Design
The CS6420 is ultimately only one part of a bigger
full-duplex hands-free system. In order for that sys-
tem to work well, it needs to be properly balanced.
The distribution of the system gains will make or
break the echo canceller. In order to judge perfor-
mance, however, the system integrator must be
armed with the means to test the product.
Gain Structure
The distribution of the system gains is an important
design consideration to keep in mind. Gain distri-
bution is an intricate balancing act where the sys-
tem integrator tries to maximize dynamic range
while minimizing noise, and at the same time, get-
ting excellent echo canceller performance.
CS6420
DS205PP2