EVAL-AD7986EBZ Analog Devices Inc, EVAL-AD7986EBZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD7986EBZ
• Description: 18-Bit A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7986EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD7986
• Kit Contents: Board
• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 2M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 29mW @ 2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7986
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7986 devices are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7986 devices is
shown in Figure 29, and the corresponding timing is given in
Figure 30.
With SDI high, a rising edge on CNV initiates a conversion, selects
the CS mode, and forces SDO to high impedance. In this mode,
CNV must be held high during the conversion phase and the
subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
SDO
ACQUISITION
CNV
SDI
SCK
(n – 1)
t
SSDICNV
t
HSDICNV
CONVERSION (n – 1)
END DATA (n – 2)
t
EN
16
t
DATA
2
t
CONV
17
1
18
SDI
0
Figure 30. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Figure 29. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
AD7986
t
(I/O QUIET
HSDO
CNV
SCK
TIME)
t
EN
t
CYC
SDO
ACQUISITION (n)
17
1
Rev. B | Page 21 of 28
BEGIN DATA (n – 1)
SDI
16
2
t
ACQ
AD7986
15
CNV
SCK
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7986 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that it has an acceptable hold time. After
the 18
another AD7986 can be read.
t
t
HSDO
DSDO
SDO
th
SCK falling edge, SDO returns to high impedance and
(QUIET
TIME)
CS2
CS1
CONVERT
DATA IN
CLK
DIGITAL HOST
t
QUIET
t
DIS
END DATA (n – 1)
CONVERSION (n)
16
2
t
DATA
17
t
1
CONV
t
SCK
18
0
t
(I/O QUIET
DIS
TIME)
ACQUISITION
AD7986
(n + 1)