EVAL-AD7985EBZ Analog Devices Inc, EVAL-AD7985EBZ Datasheet - Page 19

• Manufacturer Part Number: EVAL-AD7985EBZ
• Description: 16-Bit A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7985EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD7985
• Kit Contents: Board
• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 2.5M
• Data Interface: SPI™, QSPI™, MICROWIRE™, and DSP
• Inputs Per Adc: 1 Differential
• Input Range: 0 ~ 5 V
• Power (typ) @ Conditions: 15.5mW @ 2.5MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7985
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7985 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 26, and the corresponding timing is given in
Figure 27.
With SDI tied to VIO, a rising edge on CNV initiates a con-
version, selects CS mode, and forces SDO to high impedance.
When a conversion is initiated, it continues until completion,
irrespective of the state of CNV. This can be useful, for example,
to bring CNV low to select other SPI devices, such as analog
multiplexers; however, CNV must be returned high before the
ACQUISITION
SDI = 1
CNV
(n – 1)
SCK
SDO
t
DIS
END DATA (n – 2)
CONVERSION (n – 1)
t
EN
t
DATA
14
2
>
t
15
t
CONV
CONV
1
Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
16
0
t
(I/O QUIET
DIS
TIME)
VIO
t
CYC
SDI
t
EN
AD7985
CNV
SCK
15
1
Rev. A | Page 19 of 28
ACQUISITION (n)
14
2
SDO
t
ACQ
BEGIN DATA (n – 1)
13
minimum conversion time elapses and then held high for the
maximum possible conversion time to avoid the generation of
the busy signal indicator.
When the conversion is complete, the AD7985 enters the
acquisition phase and powers down. When CNV goes low, the
MSB is output onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided that it has an acceptable hold time. After the 16
SCK falling edge or when CNV goes high (whichever occurs
first), SDO returns to high impedance.
t
t
HSDO
DSDO
CONVERT
DATA IN
CLK
DIGITAL HOST
(I/O QUIET
TIME)
t
QUIET
t
DIS
t
CONVERSION (n)
END DATA (n – 1)
CNVH
14
t
2
DATA
t
CONV
15
1
t
SCK
16
0
t
(I/O QUIET
DIS
TIME)
AD7985
ACQUISITION
(n + 1)
th