AD9269-80EBZ Analog Devices Inc, AD9269-80EBZ Datasheet - Page 19

• Manufacturer Part Number: AD9269-80EBZ
• Description: A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9269-80EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9269
• Kit Contents: Software, Evaluation Board
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 80M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 224.6mW @ 80MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9269
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
The AD9269 dual-channel ADC design can be used for diversity
reception of signals, where the ADCs are operating identically on
the same carrier but from two separate antennae. The ADCs can
also be operated with independent analog inputs. The user can
sample any f
appropriate low-pass or band-pass filtering at the ADC inputs
with little loss in ADC performance. Operation to 300 MHz
analog input is permitted, but it occurs at the expense of
increased ADC noise and distortion.
In nondiversity applications, the AD9269 can be used as a base-
band or direct downconversion receiver, in which one ADC is
used for I input data and the other is used for Q input data.
The AD9269 incorporates an optional, integrated dc correction
and quadrature error correction block (QEC) that can correct
for dc offset, gain, and phase mismatch between the two channels.
This functional block can be very beneficial to complex signal
processing applications such as direct conversion receivers.
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD9269 are accomplished
using a 3-wire SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9269 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors in
the preceding stage. The quantized outputs from each stage are
combined into a final 16-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with a
new input sample while the remaining stages operate with pre-
ceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the CMOS output buffers. The output buffers
are powered from a separate (DRVDD) supply, allowing adjust-
ment of the output voltage swing. During power-down, the output
buffers go into a high impedance state.
S
/2 frequency segment from dc to 200 MHz, using
Rev. 0 | Page 19 of 40
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9269 is a differential switched-
capacitor circuit designed for processing differential input signals.
This circuit can support a wide common-mode range while main-
taining excellent performance. By using an input common-mode
voltage of midsupply, users can minimize signal-dependent errors
and achieve optimum performance.
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 38). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current injected from the output stage of the
driving source. In addition, low Q inductors or ferrite beads can
be placed on each leg of the input to reduce high differential
capacitance at the analog inputs and, therefore, achieve the
maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end
at high IF frequencies. Either a shunt capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter at the
input to limit unwanted broadband noise. Refer to the AN-742
Application Note, Frequency Domain Response of Switched-
Capacitor ADCs; the AN-827 Application Note, A Resonant
Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs (see www.analog.com); and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D
(Volume 39, April 2005) for more information. In general, the
precise values depend on the application.
VIN+x
VIN–x
Figure 38. Switched-Capacitor Input Circuit
C
C
PAR
PAR
H
H
S
S
C
C
SAMPLE
SAMPLE
S
S
H
H
Converters”
AD9269