EVK-CONNECT-010 DENSITRON, EVK-CONNECT-010 Datasheet
EVK-CONNECT-010
Specifications of EVK-CONNECT-010
Related parts for EVK-CONNECT-010
EVK-CONNECT-010 Summary of contents
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... OLED DISPLAY MODULE Application Notes PRODUCT DD-160128FC-1A/2A with EVK board NUMBER Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data ...
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... TABLE OF CONTENTS 1 EVK SCHEMATIC.......................................................................................................... 4 2 TIMING CHARACTERISTICS .................................................................................... 6 3 CONNECTION BETWEEN OLED AND EVK ......................................................... 11 4 HOW TO USE THE DD-160128FC-1A/2A ................................................................. 15 4 ECOMMENDED NITIAL CODE FOR DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data 80 .................................................... 15 INTERFACE REV. B Page ...
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... REVISION RECORD Rev. Date Page Chapt Sep Jan 09 DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data Comment First Issue Second Issue REV. B ECR no. Page ...
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... EVK Schematic DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data REV. B Page ...
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... Please ground the unused data pins Note2: If you do not use RGB Interface, please ground VSYNC, HSYNC, Enable, DOTCLK and floating VSYNCO. Note3: If you do not use VDDIO, please connect (VDD). DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data REV. B Page ...
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... All the timing reference is 10% and 90% of VDD Table 1 80-Series MPU Parallel Interface Timing Characteristics (Write) Figure 1 80-Series MPU parallel Interface Timing Diagram (Write) DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data (VDD = 2.8V 25˚C) CONDITION MIN MAX 5 ‐ ...
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... All the timing reference is 10% and 90% of VDD Table 2 80-Series MPU Parallel Interface Timing Characteristics (Read) Figure 2 80-Series MPU parallel Interface Timing Diagram (Read) DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data (VDD = 2.8V 25˚C) CONDITION MIN MAX 5 ‐ ...
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... All the timing reference is 10% and 90% of VDD Table 3 6800-Series MPU Parallel Interface Timing Characteristics (Write) Figure 3 6800-Series MPU parallel Interface Timing Diagram (Write) DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data (VDD = 2.8V 25˚C) CONDITION MIN MAX 5 ‐ ...
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... All the timing reference is 10% and 90% of VDD Table 4 80-Series MPU Parallel Interface Timing Characteristics (Read) Figure 4 6800-Series MPU parallel Interface Timing Diagram (Read) DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data (VDD = 2.8V 25˚C) CONDITION MIN MAX 10 ‐ ...
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... CSB hold timing tCSH All the timing reference is 10% and 90% of VDD Table 5 SPI Interface Timing Characteristics Figure 5 SPI Interface Timing Characteristics DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data (VDD = 2.8V 25˚C) CONDITION MIN MAX ‐ ...
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... Connection Between OLED and EVK Figure 6 EVK PCB and DD-160128FC-1A/2A Module DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data REV. B Page ...
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... The SEPS525F is a COF type package, which means that the connect pads are on the top of the display connector. When the EVK and display are assembled, finally push the locking pad to hold the display in place, see Figure 6 and Figure 7. User can use wires to connect the EVK with the system. The example is shown below in figure 8; DD-160128FC-1A/2A Product No. Copyright © ...
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... Figure 8 control MCU (not supplied) connected with EVK Note 1：It is the external most positive voltage supply. In this sample it is connected to power supply. 6. Power down and Power up Sequence To protect OLED panel and to extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off ...
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... Clear Screen 5. Power Delay 100ms (when V is stable Send Display on command Power down Sequence: 1. Send Display off command 2. Power down Delay 100ms 4. Power down VDD and VDDIO DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data REV. B Page ...
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... Recommended Initial code for 80 interface write_c(0x06); // Display off write_d(0x00); write_c(0x02); // OSC_CTL write_d(0x01); write_c(0x03); // CLOC_DIV write_d(0x30); // 115Hz write_c(0x04); // REDUCE_CURRENT write_d(0x00); write_c(0x80); // IREF DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data RES#=0 Delay 100ms RES#=1 Start Display REV. B Page ...
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... DISPLAY START LINE write_d(0x00); write_c(0x2e); // D1_DDRAM_FAC write_d(0x00); write_c(0x2f); // D1_DDRAM_FAR write_d(0x00); write_c(0x31); // D2_DDRAM_FAC write_d(0x00); write_c(0x32); // D2_DDRAM_FAR write_d(0x00); write_c(0x33); // SCR1_FX1 write_d(0x00); write_c(0x34); // SCR1_FX2 write_d(0x9f); write_c(0x35); // SCR1_FY1 write_d(0x00); write_c(0x36); // SCR1_FY1 DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data REV. B Page ...
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... MEMORY_ACCESSPOINTER X write_d(0x00); write_c(0x22); for(i=0;i<128;i++) { for(j=0;j<160;j++) { write_d(0xfc); write_d(0xfc); write_d(0xfc Recommended Initial Code and Sub Function Note：1.For 80 series CPU interface. 2. For 8bits Ttiple Transfer 262K support. DD-160128FC-1A/2A Product No. Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data REV. B Page ...