AFCT-57V6AUSZ Avago Technologies US Inc., AFCT-57V6AUSZ Datasheet - Page 6

• Manufacturer Part Number: AFCT-57V6AUSZ
• Description: 1.25GBd ZX SFP 80km LC -40/85
• Manufacturer: Avago Technologies US Inc.

Specifications of AFCT-57V6AUSZ

• Data Rate: 1.25Gbd
• Wavelength: 1550nm
• Applications: Ethernet
• Voltage - Supply: 2.97 V ~ 3.63 V
• Connector Type: LC Duplex
• Mounting Type: SFP
• Optical Fiber Type: TX/RX
• Data Transfer Rate: 1250Mbps
• Optical Rise Time: 0.26ns
• Optical Fall Time: 0.26ns
• Operating Temperature Classification: Industrial
• Peak Wavelength: 1550/1600nm
• Package Type: SFP
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Mounting: Snap Fit To Panel
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
A brief description of all of the electrical connector pins follows. The connector has staged contacts, so that hot-plug-
ging can be performed. See Table 10.
Table 10. Pinout.
Hot-Plugging Sequence
The ground, VCC and other pins designated as the se-
quence (1) pins engage first during hot-plugging. The
sequence (2) pins connect second during hot-plugging
followed by the sequence (3) pins. Conversely, when
the module is unplugged from the host system, the se-
quence (3) pins disengages before the sequence (2) pins
disengages and then followed by the sequence (1) pins.
Inserting or removing the AFCT-57V6USZ will disrupt
data transmission. This disruption occurs when the
downstream receiver (e.g. deserializer phase-lock-loop)
resynchronizes to a different bitstream signal. When this
occurs, the downstream system will recognize the asso-
ciated error (e.g. comma detect, loss-of-light, disparity,
CRC, and frame errors).
It is the responsibility of the system integrator to assure
that no thermal, energy, or voltage hazard exists during
the hot-plug-unplug sequence. It is also the responsibility
of the system integrator and end-user to minimize static
electricity and the probability of ESD events by careful
design.
6
Pin No.
1
2
3
4
5
6
7
8
9
10
Sequence
1
3
3
3
3
3
3
3
1
1
Description
VeeT
TX_FAULT
TX_DISABLE
MOD_DEF[2]
MOD_DEF[1]
MOD_DEF[0]
RATE_SELECT
RX_LOS
VeeR
VeeR
Figure 3. SFP Transceiver Electrical Pad Layout
20
19
18
17
16
15
14
13
12
11
Pin No
11
12
13
14
15
16
17
18
19
20
VeeT
TD-
TD+
VeeT
VccT
VccR
VeeR
RD+
RD-
VeeR
Top of Board
Sequence
1
3
3
1
2
2
1
3
3
1
Description
VeeR
RD-
RD+
VeeR
VccR
VccT
VeeT
TD+
TD-
VeeT
10
1
2
3
4
5
6
7
8
9
(as view through top of board)
MOD_DEF[2]
MOD_DEF[1]
VeeT
TX_FAULT
TX_DISABLE
RATE_SELECT
RX_LOS
VeeR
VeeR
MOD_DEF[0]
Bottom of Board