ADNS-2030 Avago Technologies US Inc., ADNS-2030 Datasheet - Page 7

• Manufacturer Part Number: ADNS-2030
• Description: Optical Mouse Sensor,DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-2030

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Recommended Operating Conditions
Parameter
Operating Temperature
Power Supply Voltage
Power Supply Rise Time
Supply Noise
Clock Frequency
Serial Port Clock Frequency
Resonator Impedance
Distance from Lens Reference
Plane to Surface
Speed
Acceleration
Light Level onto IC
SDIO Read Hold Time
SDIO Serial Write-write Time
SDIO Serial Write-read Time
SDIO Serial Read-write Time
SDIO Serial Read-read Time
Data Delay after PD ↓
SDIO Write Setup Time
PD Pulse Width
(to power down the chip)
PD Pulse Width
(to reset the serial port)
Frame Rate
Bin Resistor

Symbol
T
V
V
V
f
SCLK
X
Z
S
A
t
t
t
t
t
t
t
t
t
FR
R1
IRR
CLK
HOLD
SWW
SWR
SRW
SRR
COMPUTE
SETUP
PDW
PD
A
DD
RT
N
RES
INC
Minimum
0
3.0
17.4
2.3
0
80
100
100
100
100
120
120
3.2
60
700
100
15K
Typical
3.3
18.0
2.4
1500
15K
Maximum
40
3.6
100
30
18.7
f
55
2.5
14
0.15
25,000
30,000
37K
CLK
/4
Units
°C
Volts
ms
mV
MHz
MHz
Ω
mm
in/sec
g
mW/m
µs
µs
µs
ns
ns
ms
ns
µs
µs
frames/s
Ω
2
Notes
Peak to peak @27 MHz bandwidth
Set by ceramic resonator
Results in ±0.2 mm DOF
(See Figure 9.)
@ frame rate = 1500 fps
@ frame rate = 1500 fps
λ = 639 nm
λ = 875 nm
Hold time for valid data
(Refer to Figure 27.)
Time between two write commands
(Refer to Figure 30.)
Time between write and read
operation (Refer to Figure 31.)
Time between read and write
operation (Refer to Figure 32.)
Time between two read commands
(Refer to Figure 32.)
After t
data from first image after PD ↓.
Note that an additional 75 frames
for AGC stabilization may be required
if mouse movement occurred while
PD was high. (Refer to Figure 11.)
Data valid time before the rising of
SCLK (Refer to Figure 25.)
Pulse width to initiate the power down
cycle @1500 fps (Refer to Figure 13.)
Pulse width to reset the serial port
@1500 fps (but may also initiate a
power down cycle) (Refer to Figure 11.)
See Frame_Period register section
Refer to Figure 8
COMPUTE
, all registers contain