ADNS-2030 Avago Technologies US Inc., ADNS-2030 Datasheet - Page 17

• Manufacturer Part Number: ADNS-2030
• Description: Optical Mouse Sensor,DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-2030

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read Operation
A read operation, which means that data is going from the
ADNS-2030 to the microcontroller, is always initiated by the
micro-controller and consists of two bytes. The first byte
contains the address, is written by the micro-controller, and
has a “0” as its MSB to indicate data direction. The second
byte contains the data and is driven by the ADNS-2030.
The transfer is synchronized by SCLK. SDIO is changed on
falling edges of SCLK and read on every rising edge of SCLK.
Figure 26. Read operation.
Figure 27. Microcontroller to ADNS-2030 SDIO handoff.
Figure 28. ADNS-2030 to microcontroller SDIO handoff.
NOTE: The 120 ns high state of SCLK is the minimum data
hold time of the ADNS-2030. Since the falling edge of
SCLK is actually the start of the next read or write com-
mand, the ADNS-2030 will hold the state of D
SDIO line until the falling edge of SCLK. In both write and
read operations, SCLK is driven by the microcontroller.
1
Cycle #
Detail "A"
Microcontroller
to ADNS-2030
SDIO handoff
Detail "B"
ADNS-2030 to
Microcontroller
SDIO handoff
SCLK
SCLK
SDIO
1
0
SCLK
SDIO
SCLK
SDIO
A
2
6
A
Released by 2030
1
SDIO Driven by Microcontroller
3
A
5
D
0
4
A
4
60 ns, min
5
A
3
120 ns, min
R/W bit of next address
6
A
2
10 ns, max
Driven by micro
120 ns, min
A
0
0
on the
7
A
1
100 s, min
t
HOLD
A
0
8
Detail "A"
0 ns, min
The micro-controller must go to a high Z state after the last
address data bit. The ADNS-2030 will go to the high Z state
after the last data bit. (see detail “B” in Figure 29). One other
thing to note during a read operation is that SCLK will need
to be delayed after the last address data bit to ensure that
the ADNS-2030 has at least 100 µs to prepare the requested
data. This is shown in the timing diagrams below.
Serial port communications is not allowed while PD
(Power Down) is high. See “Error Detection and Recovery”
regarding re-synchronizing via PD.
D
9
7
10
D
6
Hi-Z
11
D
5
SDIO Driven by ADNS-2030
120 ns, max
12
D
0 ns, min
4
D
7
13
D
3
D
6
14
D
120 ns, max
2
15
D
1
16
D
Detail "B"
0