ACPL-K370-060E Avago Technologies US Inc., ACPL-K370-060E Datasheet - Page 12

• Manufacturer Part Number: ACPL-K370-060E
• Description: Isolated Volt/Curr Det,IEC+LF
• Manufacturer: Avago Technologies US Inc.

Specifications of ACPL-K370-060E

• Voltage - Isolation: 5000Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 30mA
• Propagation Delay High - Low @ If: 3.7µs
• Input Type: Logic
• Output Type: Open Collector
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.268", 6.81mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Considerations
The ACPL-K370/K376 optocouplers have internally tem-
perature compensated, predictable voltage and current
threshold points. This allows a single external resistor, R
to determine larger external threshold voltage levels. For
a desired external threshold voltage, V
R
calculate Rx.
V
set with two resistors, R
determined by Equations 4 and 5.
R
limiting input current during a transient condition. For
monitoring contacts of a relay or switch, the ACPL-K370/
K376 in combination with R
specific current to be conducted through the contacts for
cleaning purposes (wetting current).
The choice of which input voltage clamp level to choose
depends upon the application of this device (see Figure 4).
It is recommended that the low clamp condition be used
when possible. The low clamp condition in conjunction
with the low input current feature will ensure extremely
low input power dissipation.
In applications where dV
(such as with a static discharge), a series resistor, R
should be connected in series with V
the detector IC from destructive high surge currents. The
recommended value for R
drop in V
of 240 :. In addition, it is recommended that a ceramic
disc bypass capacitor of 0.01 PF be placed between pins 5
and 8 to reduce the effect of power supply noise.
For interfacing ac signals to TTL systems, output low pass
filtering can be performed with a pull-up resistor of 1.5 k:
and 20 PF capacitor. This application requires a Schmitt
trigger gate to avoid slow rise time chatter problems.
For AC input applications, a filter capacitor can be placed
across the DC input terminals for either signal or transient
filtering.
V
Figure 13. External threshold voltage level selection.
12
±
x
+
X
value is shown in Figure 12. Equation 1 can be used to
and V
can provide over-current transient protection by
–
CC
R
voltage threshold levels can be simultaneously
X
(between Pin 8 and V
R
P
V
I
TH±
TH±
X
and R
1
2
3
4
CC
CM
X
AC1
DC+
DC–
AC2
is 240 : per volt of allowable
and R
/dt may be extremely large
ISOLATION
P,
BARRIER
as shown in Figure 13 and
CC
P
) with a minimum value
CC
can be used to allow a
GND
V
and pin 8 to protect
NC
V
±
CC
O
, the approximate
8
7
6
5
GND
R
C
L
L
CC
V
V
X
CC
O
,
,
Either AC (pins 1 and 4) or DC (pins 2 and 3) input can be
used to determine external threshold levels. For single
specifically selected external threshold voltage level V
V
R
For dual specifically selected external threshold voltage
levels, V
selection. Two equations can be written:
V
V
Solving these equations for R
two expressions:
R
R
where
V
levels, and values for V
data sheet.
Equations 4 and 5 are valid only if the conditions of
Equations 6 or 7 are met. With the V
the denominator of Equation 4 is checked to see if it is
positive or negative. If it is positive, then the following
ratios must be met:
V
V–
Conversely, if the denominator of Equation 4 is negative,
then the following ratios must hold:
V
V–
Refer to Application Note 1004 for more application infor-
mation and worked out examples.
–
X
+
–
X
P
+
+
+
, R
= R
=
=
= R
=
≥
≤
and V
X
I
V
V
V
V
V
TH+
can be determined without use of R
x
x
V
TH+
TH–
TH+
TH–
+(–)
I
TH+
( I
( I
TH–
+
I
TH+
TH–
(V
TH+(–)
–
and V
– V
and
and
(V
(V
TH–
are the desired external voltage threshold
V
+
+
–
TH+(–)
+
TH–
) – V
) – I
– V
V
V
V
V
V
V
–
R
R
+
–
+
–
, the use of R
TH+
TH–
P
P
(V
TH–
– V
– V
TH–
– V
– V
TH+
+
) + V
) – V
) + I
TH–
TH–
) + V
TH+
TH+
(V
(V
TH±
TH+
–
TH–
<
>
TH–
TH+
TH+
)
)
I
I
I
I
and I
TH+
TH–
TH+
TH–
(V
X
(V
and R
TH+
X
–
)
TH±
and R
– V
P
TH±
are found from the
yields the following
+
)
P
and I
will permit this
P
via:
TH±
Equation 1
Equation 2
Equation 3
Equation 4
Equation 5
Equation 6
Equation 7
values,
+
or