ACPL-7970-500E Avago Technologies US Inc., ACPL-7970-500E Datasheet - Page 13

• Manufacturer Part Number: ACPL-7970-500E
• Description: IsolatedSigmaDelta Mod, TR+IEC+LF
• Manufacturer: Avago Technologies US Inc.
• Series: -r
• Type: Sigma-Delta Modulatorr

Specifications of ACPL-7970-500E

• Operating Supply Voltage: 5.5 V
• Supply Current: 8 mA at 5 V
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: DIP-8 Gull Wing
• Input Voltage Range (max): + 200 mV
• Voltage - Isolation: 5000Vrms
• Input Type: DC
• Voltage - Supply: 3 V ~ 5.5 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Details

Table 10. Input voltage with ideal corresponding density of 1s at modulator data output, and ADC code.
Notes:
1. With bipolar offset binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input until
2. Ideal density of 1s at modulator data output can be calculated with V
Digital Filter
A digital filter converts the single-bit data stream from
the modulator into a multi-bit output word similar to
the digital output of a conventional A/D converter. With
this conversion, the data rate of the word output is also
reduced (decimation). A Sinc
Note: In applications, 1 PF/0.1 PF bypass capacitors are recommended to connect between pins V
and between pins V
Figure 17. Typical application circuit with a Sinc
13
Analog Input
Full-Scale Range
+Full-Scale
+Recommended Input Range
Zero
–Recommended Input Range
–Full-Scale
CURRENT
INPUT
the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input.
× 65,536 + 32,768, assuming a 16-bit unsigned decimation filter.
R
SHUNT
DD2
1 F
ISOLATED
and GND2 of the ACPL-7970.
GND1
5 V
0.1 F
3
filter is recommended to
V
V
V
GND1
DD1
IN+
IN–
3
filter.
ACPL-7970
ISOLATION
Voltage Input
640 mV
+320 mV
+200 mV
0 mV
-200 mV
-320 mV
BARRIER
MDAT
MCLK
GND2
V
DD2
0.1
ISOLATED
5 V/3.3 V
F
GND2
NON-
IN
Density of 1s
100%
81.25%
50%
18.75%
0%
/640 mV + 50%; similarly, the ADC code can be calculated with (V
work together with the ACPL-7970. With 256 decimation
ratio and 16-bit word settings, the output data rate is 39
kHz (= 10 MHz/256). This filter can be implemented in an
ASIC, an FPGA or a DSP. Some of the ADC codes with cor-
responding input voltages are shown in Table 5.
1 F
V
CLOCK
DATA
GND
DD
SINC
3
FILTER
ADC Code (16-bit unsigned decimation)
65,535
53,248
32,768
12,288
0
DD1
SDAT
SCLK
and GND1,
CS
3-WIRE
SERIAL
INTERFACE
IN
/640 mV)