USBN9604-28MX National Semiconductor, USBN9604-28MX Datasheet - Page 35

• Manufacturer Part Number: USBN9604-28MX
• Description: IC,Bus Controller,SOP,28PIN
• Manufacturer: National Semiconductor

Specifications of USBN9604-28MX

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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7.0 Register Set
EOP
End of Packet. A valid EOP sequence was detected on the USB. It is used when this device has initiated a Remote wake-up
sequence to indicate that the Resume sequence has been acknowledged and completed by the host. This bit is cleared when
the register is read.
SD3
Suspend Detect 3 mS. This bit is set after 3 mS of IDLE is detected on the upstream port, indicating that the device should
be suspended. The suspend occurs under firmware control by writing the suspend value to the Node Functional State (NF-
SR) register. This bit is cleared when the register is read.
SD5
Suspend Detect 5 mS. This bit is set after 5 mS of IDLE is detected on the upstream port, indicating that this device is per-
mitted to perform a remote wake-up operation. The resume may be initiated under firmware control by writing the resume
value to the NFSR register. This bit is cleared when the register is read.
RESET
This bit is set when 2.5 S of SEO is detected on the upstream port. In response, the functional state should be reset (NFS
in the NFSR register is set to RESET), where it must remain for at least 100 S. The functional state can then return to Op-
erational state. This bit is cleared when the register is read.
RESUME
Resume signalling is detected on USB when the device is in Suspend state (NFS in the NFSR register is set to SUSPEND),
and a non IDLE signal is present on USB, indicating that this device should begin its wake-up sequence and enter Opera-
tional state. This bit is cleared when the register is read.
7.1.8
A bit set to 1 in this register enables automatic setting of the ALT bit in the MAEV register when the respective event in the
ALTEV register occurs. Otherwise, setting ALT bit is disabled.
7.1.9
TXFIFO
Transmit FIFO. These bits are a copy of the TX_DONE bits from the corresponding Transmit Status (TXSx) registers. The
bits are set when the IN transaction for the corresponding transmit endpoint is complete. The bits are cleared when the cor-
responding TXSx register is read.
TXUDRRN
Transmit Underrun. These bits are copies of the respective TX_URUN bits from the corresponding TXSx registers. When-
ever any of the Transmit FIFOs underflow, the respective TXUDRRN bit is set. These bits are cleared when the correspond-
ing Transmit Status register is read.
Alternate Mask Register (ALTMSK)
Transmit Event Register (TXEV)
TXFIFO3 TXFIFO2 TXFIFO1
bit 7
1. Since Endpoint 0 implements a store and forward principle, an underrun condition for
bit 7
0
0
FIFO0 cannot occur. This results in the TXUDRRN0 bit always being read as 0.
(Continued)
bit 6
TXUDRRN3-0
0
r
bit 6
0
bit 5
Same Bit Definition as ALTEV Register
0
bit 5
0
FIFO0
bit 4
r/w
0
1
bit 4
0
34
TXFIFO3
bit 3
0
bit 3
0
TXFIFO2
bit 2
bit 2
TXFIFO3-0
0
0
r
TXFIFO1
bit 1
0
bit 1
0
bit 0
FIFO0
bit 0
-
-
0