USBN9604-28MX National Semiconductor, USBN9604-28MX Datasheet - Page 28

• Manufacturer Part Number: USBN9604-28MX
• Description: IC,Bus Controller,SOP,28PIN
• Manufacturer: National Semiconductor

Specifications of USBN9604-28MX

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.0 Functional Description
(Continued)
TCOUNT
Transmit FIFO Count. This value indicates how many empty bytes can be filled within the transmit FIFO. This value is ac-
cessible by firmware via the TxSx register.
Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3)
The Receive FIFOs for the Endpoints 2, 4 and 6 support bulk, interrupt and isochronous USB packet transfers larger than
the actual FIFO size. If the packet length exceeds the FIFO size, the firmware must read the FIFO contents while the USB
packet is being received on the bus. Figure 22 shows the detailed behavior of receive FIFOs.
FLUSH (Resets RXRP and RXWP)
RXRP
RFxS - 1
0x0
RCOUNT = RXWP - RXRP
+
+
Rx FIFO X
RXWP
+
RXFL = RXRP - RXWP (= RFxS - RCOUNT)
Figure 22. Rx FIFO Operation
RFxS
Receive FIFO x Size. This is the total number of bytes available within the FIFO.
RXRP
Receive Read Pointer. This pointer is incremented with every read of the firmware from the receive FIFO. This pointer wraps
around to zero if RFxS is reached. RXRP is never incremented beyond the value of RXWP.
If an attempt is made to read more bytes than are actually available (FIFO underrun), the last byte is read repeatedly.
RXWP
Receive Write Pointer. This pointer is incremented every time the Endpoint Controller writes to the receive FIFO. This pointer
wraps around to zero if RFxS is reached.
An overrun condition occurs if RXRP equals RXWP and an attempt is made to write an additional byte.
RXFL
Receive FIFO Level. This value indicates how many more bytes can be received until an overrun condition occurs with the
next write to the FIFO.
A FIFO warning is issued if RXFL decreases to a specific value. The respective WARNx bit in the FWR register is set if RXFL
is equal to or less than the number specified by the RFWL bit in the RXCx register.
RCOUNT
Receive FIFO Count. This value indicates how many bytes can be read from the receive FIFO. This value is accessible by
firmware via the RXSx register.
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