SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 9

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit(s)
0x00 - 0x1F
0x20 - 0x27
0x28 - 0x2E
0x2F
0x30 - 0x3F
Bit(s)
0x00 - 0x1F
0x20 - 0x3FF
Bit(s)
0x1F
0x1E
0x1D - 0x1B
0x1A - 0x18
0x17
0x16
0x15
0x14 - 0x12
0x11
0x10
0xF - 0x9
0x8
0x7
0x6 - 0x0
A4
1
1
1
1
1
1
Note 5: The TDI_SM LFSR result and seed registers require two sequential reads/writes for each register pair.
Note 6: The index register is used to set the individual address pointers. Writine to the index register will set each of the individual address pointers (TDO_SM,
TDI_SM, Expected, and Mask). The individual address pointers will automatically increment with each long word read from TDI_SM or each long word written to
the TDO_SM, Expected, or Mask memory spaces.
Note 7: The actual address is calculated from the base address of the memory area plus the content of its address pointer.
Note 8: The upper two bytes of each vector is ignored. These have been inserted to make the space align on long word boundaries.
Note 9: Count must be greater than zero if the Header/Trailer Usage bits are not equal to "000" or "111".
A3
0
0
0
1
1
1
A2
1
1
1
0
0
0
A1
0
1
1
0
0
1
A0
1
0
1
0
1
0
Function
Macro Index
Macro 1
Macro 2
Macro 3 . . .
Macro 16
Sequencer Index
Sequencer
Scan Bridge Support Index
Scan Bridge Support
Function
Length (maximum of 4G)
Macro Number (1 of 256) Room for scaleability
Reserved
Preloaded data / Load-on-the-fly (LotF)
Reserved
Function
32-bit count (Note 9)
124 bytes (992 bits) header/trailer data
Function
Compare
Use Mask / Compare full length of vector (not including header/trailer)
Post-shift TCK_SM Count
Pre-shift TCK_SM Count
Sync Bit Support Enable
Macro Structure Bit 8 Enable (Ignored for the shift macros with or without capture)
Macro Structure bit 7 Enable (Ignored for the shift macros with or without capture)
Header/Trailer Usage
Macro Type bit 1
Macro Type bit 0
Last 7 TMS_SM bits
Presented during the falling edge of TCK_SM at terminal count during a Shift macro. Use in the same
manner as other TMS bits for State and BIST Macros.
Loop Bit if Macro type is Shift (for 1149.1 it would be a 0) or BIST
First 7 TMS_SM Bits (LSB is first bit to be shifted out of TMS_SM)
TABLE 6. Header/Trailer Structure
TABLE 5. Vector Structure
TABLE 7. Macro Structure
Base Address
N/A
0 x 788
0 x 789
0 x 78A . . .
0 x 797
N/A
0 x 798
N/A
0 x 7B8
9
Long Word Index
N/A
0x0
0x1
0x2 . . .
0xF
N/A
0x0 - 0x1F
N/A
0x0 - 0x3F
Structure/Size
16-bit Register
Tables 7, 8, 9
16-bit Register
Table 10
16-bit Register
Table 11
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