SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 25

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note 16: Reserved Vector x Interrupt Enable for future growth for the number of vectors.
Note 17: Drivers should not allow Sequencer Interrupt Enable and Vector x Interrupt Enable to be set at same time. Sequencer Interrupt Enable has priority over
the Vector x Interrupt Enable.
Note 18: Half full or half empty designates 56 long words.
TDO Half-empty Interrupt Enable TDO_SM memory space half empty interrupt enable
TDO Empty Interrupt Enable
TDI Full Interrupt Enable
TDI Half-full Interrupt Enable
Sequencer Interrupt Enable
Vector Interrupt Enable<2:0>
Bit(s)
15:13
7:3
2:0
12
11
10
9
8
'000'
'001'
'010'
'011'
'100'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Type
RW
RW
RW
RW
RW
RW
RO
RO
Reserved
TDO Half-empty Interrupt Enable (Note
18)
TDO Empty Interrupt Enable
TDI Full Interrupt Enable
TDI Half-full Interrupt Enable (Note 18)
Sequencer Interrupt Enable (Note 17)
Reserved Vector x Interrupt Enable
(Note 16)
Vector x Interrupt Enable (Note 17)
TABLE 21. Interrupt Control Register (INTCTRL) ($02)
Enable TDO_SM memory space half empty interrupt
Disable TDO_SM memory space half empty interrupt
TDO_SM memory space empty interrupt enable
Enable TDO_SM memory space empty interrupt
Disable TDO_SM memory space empty interrupt
TDI_SM memory space full interrupt enable
Enable TDI_SM memory space full interrupt
Disable TDI_SM memory space full interrupt
TDI_SM memory space half full interrupt enable
Enable TDI_SM memory space half full interrupt
Disable TDI_SM memory space half full interrupt
Sequencer activity complete interrupt enable
Enable Sequencer activity complete interrupt
Disable Sequencer activity complete interrupt
Vector "x" complete interrupt enable, where "x" is the vector number, a binary encoding
of bits <2:0>. Only vector interrupts1 through 4 are valid. Vector interrupts 5 through 7
reserved for future use.
No vector interrupt enabled
Vector 1 interrupt enabled
Vector 2 interrupt enabled
Vector 3 interrupt enabled
Vector 4 interrupt enabled
Field
25
Address Offset
0
0
0
0
0
0
0
0
Reset Value
00000b
000b
000b
0b
0b
0b
0b
0b
Reset Source
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
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