PIC24FJ64GA006T-I/PT Microchip Technology, PIC24FJ64GA006T-I/PT Datasheet - Page 42
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PIC24FJ64GA006T-I/PT
Manufacturer Part Number
PIC24FJ64GA006T-I/PT
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ64GA006-IPT.pdf
(240 pages)
3.PIC24FJ64GA006-IPT.pdf
(22 pages)
Specifications of PIC24FJ64GA006T-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, AC164127, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GA006T-I/PT
Manufacturer:
MICROCHIP
Quantity:
1 000
Company:
Part Number:
PIC24FJ64GA006T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC24FJXXXGA0XX
5.4
5.4.1
If it is determined that the programming executive is
not present in executive memory (as described
in Section 4.2 “Confirming the Presence of the
Programming Executive”), it must be programmed
into executive memory using ICSP, as described in
Section 3.0 “Device Programming – ICSP”.
TABLE 5-5:
DS39768D-page 42
Step 1: Exit Reset vector and erase executive memory.
Step 2: Initialize pointers to read Diagnostic and Calibration Words for storage in W6-W13.
Step 3: Repeat this step 8 times to read Diagnostic and Calibration Words, storing them in W registers, W6-W13.
Step 4: Initialize the NVMCON to erase executive memory.
Step 5: Initialize Erase Pointers to first page of executive and then initiate the erase cycle.
Step 6: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
Command
(Binary)
00000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0000
Programming the Programming
Executive to Memory
OVERVIEW
PROGRAMMING THE PROGRAMMING EXECUTIVE
000000
040200
000000
200800
880190
207F00
2000C2
000000
BA1931
000000
000000
240420
883B00
200800
880190
200001
000000
BB0881
000000
000000
A8E761
000000
000000
040200
000000
803B02
883C22
000000
<VISI>
000000
(Hex)
Data
NOP
GOTO
NOP
MOV
MOV
MOV
MOV
NOP
TBLRDL
NOP
NOP
MOV
MOV
MOV
MOV
MOV
NOP
TBLWTL
NOP
NOP
BSET
NOP
NOP
GOTO
NOP
MOV
MOV
NOP
Clock out contents of the VISI register.
NOP
0x200
#0x80, W0
W0, TBLPAG
#0x07F0, W1
#0xC, W2
[W1++].[W2++]
#0x4042, W0
W0, NVMCON
#0x80, W0
W0, TBLPAG
#0x0, W1
W1, [W1]
NVMCON, #15
0x200
NVMCON, W2
W2, VISI
Storing the programming executive to executive
memory is similar to normal programming of code
memory. Namely, the executive memory must be
erased, and then the programming executive must be
programmed 64 words at a time. Erasing the last page
of executive memory will cause the FRC oscillator
calibration settings and device diagnostic data in the
Diagnostic and Calibration Words, at addresses
8007F0h to 8007FEh, to be erased. In order to retain
this calibration, these memory locations should be read
and stored prior to erasing executive memory. They
should then be reprogrammed in the last words of pro-
gram memory. This control flow is summarized in
Table 5-5.
Description
© 2008 Microchip Technology Inc.