PIC18LF2682-I/SP Microchip Technology, PIC18LF2682-I/SP Datasheet - Page 336
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PIC18LF2682-I/SP
Manufacturer Part Number
PIC18LF2682-I/SP
Description
80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF2682-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
80KB (40K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 336 of 484
- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
23.9.1
The microcontroller clock frequency generated from a
PLL circuit is subject to a jitter, also defined as Phase
Jitter or Phase Skew. For its PIC18 Enhanced micro-
controllers, Microchip specifies phase jitter (P
being 2% (Gaussian distribution, within 3 standard
deviations, see parameter F13 in Table 27-7) and Total
Jitter (T
FIGURE 23-5:
Once these considerations are taken into account, it is
possible to show that the relation between the jitter and
the total frequency error can be defined as:
EQUATION 23-4:
where jitter is expressed in terms of time and NBT is the
Nominal Bit Time.
DS39761C-page 336
jitter
Nominal Clock
Clock with Jitter
CAN bit Time
with Jitter
) as being 2 * P
EXTERNAL CLOCK, INTERNAL
CLOCK AND MEASURABLE JITTER
IN HSPLL-BASED OSCILLATORS
Δf
=
----------------------- -
10 NBT
T
EFFECTS OF PHASE JITTER ON THE MICROCONTROLLER CLOCK
AND CAN BIT TIME
×
jitter
jitter
=
.
----------------------- -
10 NBT
2 P
×
×
jitter
jitter
) as
Phase Skew (Jitter)
CAN bit Jitter
The CAN protocol uses a bit-stuffing technique that
inserts a bit of a given polarity following five bits with the
opposite polarity. This gives a total of 10 bits transmit-
ted without re-synchronization (compensation for jitter
or phase error).
Given the random nature of the jitter error added, it can
be shown that the total error caused by the jitter tends
to cancel itself over time. For a period of 10 bits, it is
necessary to add only two jitter intervals to correct for
jitter-induced error: one interval in the beginning of the
10-bit period and another at the end. The overall effect
is shown in Figure 23-5.
For example, assume a CAN bit rate of 125 Kb/s, which
gives an NBT of 8 μs. For a 16 MHz clock generated
from a 4x PLL, the jitter at this clock frequency is:
EQUATION 23-5:
The resultant frequency error is:
EQUATION 23-6:
2
-------------------------------------- -
10
×
2%
(
×
1.25
(
8
×
×10
-------------------
16 MHz
×10
–
1
–
6
9
)
)
=
© 2009 Microchip Technology Inc.
=
3.125
-----------------
16
0.02
×10
×10
6
5 –
=
=
1.25ns
0.0031%
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