PIC18LF2682-I/SO Microchip Technology, PIC18LF2682-I/SO Datasheet - Page 93
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PIC18LF2682-I/SO
Manufacturer Part Number
PIC18LF2682-I/SO
Description
80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF2682-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
80KB (40K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2682-I/SO
Manufacturer:
Microchip Technology
Quantity:
135
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 93 of 484
- Download datasheet (9Mb)
5.5
The operation of program memory is unaffected by the
use of the extended instruction set.
Enabling the extended instruction set adds eight
additional two-word commands to the existing
PIC18 instruction set: ADDFSR, ADDULNK, CALLW,
MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These
instructions
Section 5.2.4 “Two-Word Instructions”.
5.6
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core PIC18
instructions is different. This is due to the introduction of
a new addressing mode for the data memory space.
This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
5.6.1
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented –
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset or Indexed Literal Offset mode.
© 2009 Microchip Technology Inc.
Program Memory and the
Extended Instruction Set
Data Memory and the Extended
Instruction Set
INDEXED ADDRESSING WITH
LITERAL OFFSET
are
executed
as
described
PIC18F2682/2685/4682/4685
in
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
• The file address argument is less than or equal to
Under these conditions, the file address of the instruc-
tion is not interpreted as the lower byte of an address
(used with the BSR in Direct Addressing), or as an 8-bit
address in the Access Bank. Instead, the value is
interpreted as an offset value to an Address Pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.6.2
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all byte-
oriented and bit-oriented instructions, or almost one-half
of the standard PIC18 instruction set. Instructions that
only use Inherent or Literal Addressing modes are
unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’), or include a file address of 60h or above.
Instructions meeting these criteria will continue to
execute as before. A comparison of the different possi-
ble addressing modes when the extended instruction
set is enabled in shown in Figure 5-8.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 25.2.1
“Extended Instruction Syntax”.
and
5Fh.
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
DS39761C-page 93
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