PIC18LF2682-I/SO Microchip Technology, PIC18LF2682-I/SO Datasheet - Page 167
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PIC18LF2682-I/SO
Manufacturer Part Number
PIC18LF2682-I/SO
Description
80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF2682-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
80KB (40K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2682-I/SO
Manufacturer:
Microchip Technology
Quantity:
135
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 167 of 484
- Download datasheet (9Mb)
15.2
In
ECCPR1H:ECCPR1L) register pair captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on the CCP1/ECCP1 pin (RC2 for 28/40/44-pin
devices and RD4 for 40/44-pin devices). An event is
defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture
is made, the interrupt request flag bit, CCP1IF
(PIR1<2>), is set; it must be cleared in software. If
another capture occurs before the value in the CCPR1
register pair is read, the old captured value is overwritten
by the new captured value.
15.2.1
In Capture mode, the appropriate CCP1/ECCP1 pin
should be configured as an input by setting the
corresponding TRIS direction bit.
15.2.2
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP1 module is
selected in the T3CON register (see Section 15.1.1
“CCP1 Modules and Timer Resources”).
15.2.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE or ECCP1IE interrupt enable bit clear to avoid
false interrupts. The interrupt flag bit, CCP1IF or
ECCP1IF, should also be cleared following any such
change in operating mode.
© 2009 Microchip Technology Inc.
Note:
Capture
Capture Mode
CCP1 PIN CONFIGURATION
If RC2/CCP1 or RD4/PSP4/ECCP1/P1A
is configured as an output, a write to the
port can cause a capture condition.
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT
mode,
the
CCPR1H:CCPR1L
PIC18F2682/2685/4682/4685
(or
15.2.4
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCP1M3:CCP1M0). Whenever
the CCP1 module is turned off or the CCP1 module is
not in Capture mode, the prescaler counter is cleared.
This means that any Reset will clear the prescaler
counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
15.2.5
The CAN capture event occurs when a message is
received in any of the receive buffers. When config-
ured, the CAN module provides the trigger to the CCP1
module to cause a capture event. This feature is
provided to “time-stamp” the received CAN messages.
This feature is enabled by setting the CANCAP bit of
the CAN I/O Control register (CIOCON<4>). The
message receive signal from the CAN module then
takes the place of the events on the RC2/CCP1 pin.
If this feature is selected, then four different capture
options for CCP1M<3:0> are available:
• 0100 – every time a CAN message is received
• 0101 – every time a CAN message is received
• 0110 – every 4th time a CAN message is
• 0111 – Capture mode, every 16th time a CAN
EXAMPLE 15-1:
CLRF
MOVLW
MOVWF
CCP1CON
NEW_CAPT_PS
CCP1CON
received
message is received
CCP1 PRESCALER
CAN MESSAGE TIME-STAMP
CHANGING BETWEEN
CAPTURE PRESCALERS
; Turn CCP1 module off
; Load WREG with the
; new prescaler mode
; value and CCP1 ON
; Load CCP1CON with
; this value
DS39761C-page 167
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