PIC18LF2550T-I/SO Microchip Technology, PIC18LF2550T-I/SO Datasheet - Page 5
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PIC18LF2550T-I/SO
Manufacturer Part Number
PIC18LF2550T-I/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
Specifications of PIC18LF2550T-I/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
4. Module: Interrupts
EXAMPLE 1:
© 2009 Microchip Technology Inc.
ISR @ 0x0008
Foo:
CALL Foo, FAST; store current value of WREG, BSR, STATUS for a second time
POP
:
:
RETFIEFAST
If an interrupt occurs during a two-cycle instruc-
tion that modifies the STATUS, BSR or WREG
register, the unmodified value of the register will
be saved to the corresponding Fast Return
(Shadow) register and upon a fast return from the
interrupt, the unmodified value will be restored to
the STATUS, BSR or WREG register.
For example, if a high-priority interrupt occurs
during the instruction, “MOVFF TEMP, WREG”,
the MOVFF instruction will be completed and
WREG will be loaded with the value of TEMP
before branching to ISR. However, the previous
value of WREG will be saved to the Fast Return
register during ISR branching. Upon return from
the interrupt with a fast return, the previous value
of WREG in the Fast Return register will be
written to WREG.
This results in WREG containing the value it had
before execution of “MOVFF TEMP, WREG“.
Affected instructions are:
Work around
Alternative work arounds are available for the
Assembly Language Programming and the C
Programming Language:
MOVFF Fs, Fd
Where Fd is WREG, BSR or STATUS
MOVSF Zs, Fd
Where Fd is WREG, BSR or STATUS
MOVSS [Zs], [Zd]
Where the destination is WREG, BSR or
STATUS
; clears return address of Foo call
; insert high priority ISR code here
INTERRUPT WORK AROUND – ASSEMBLY
PIC18F2455/2550/4455/4550
Assembly Language Programming
Either of two work arounds can be used:
• If any two-cycle instruction is used to modify
• As another alternative, use the work around
the WREG, BSR or STATUS register, do not
use the RETFIE FAST instruction to return
from the interrupt. Instead, save/restore
WREG, BSR and STATUS via software per
Example 9-1 in the Device Data Sheet.
Alternatively, in the case of MOVFF, use the
MOVF instruction to write to WREG instead.
For example, use:
shown in Example 1. This example overwrites
the Fast Return register by making a
dummy call to Foo with the fast option in the
high-priority service routine.
MOVF
MOVWF
instead of: MOVFF TEMP, BSR.
TEMP, W
BSR
DS80478A-page 5