PIC18LF2550T-I/SO Microchip Technology, PIC18LF2550T-I/SO Datasheet - Page 19
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PIC18LF2550T-I/SO
Manufacturer Part Number
PIC18LF2550T-I/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
Specifications of PIC18LF2550T-I/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2. Module: Timer1
12.7
Following a Timer1 interrupt and an update to the
TMR1 registers, the Timer1 module uses a falling edge
on its clock source to trigger the next register update on
the rising edge. If the update is completed after the
clock input has fallen, the next rising edge will not be
counted.
If the application can reliably update TMR1 before the
timer input goes low, no additional action is needed.
Otherwise, an adjusted update can be performed fol-
lowing a later Timer1 increment. This can be done by
monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L reg-
ister pair while the clock is low, or one-half of the period
of the clock source. Assuming that Timer1 is being
used as a Real-Time Clock, the clock source is a
32.768 kHz crystal oscillator; in this case, one-half
period of the clock is 15.25 μs.
The Real-Time Clock application code in Example 12-1
shows a typical ISR for Timer1, as well as the optional
code required if the update cannot be done reliably
within the required interval.
(Example 12-1 appears on page 18 of this errata.)
3. Module: Universal Serial Bus (USB)
© 2009 Microchip Technology Inc.
The following text, Section 12.7 “Considerations
in Asynchronous Counter Mode”, is new. It
defines the proper method to update the TMR1
registers in Asynchronous mode.
Section 12.7 is located after Section 12.6 “Using
Timer1 as a Real-Time Clock” in the data sheet.
In Section 17.2.2.8 “Internal Regulator,” the fol-
lowing corrections should be noted (changes and
added text appear in bold for the purposes of this
errata):
• In the second paragraph, the first sentence is
• In the final note box of the section, Note 2 is
corrected to read, “The regulator is disabled by
default and can be enabled through the
VREGEN Configuration bit.”
The sentence originally stated, “The regulator is
enabled by default and can be disabled through
the VREGEN Configuration bit.”
corrected to read, “V
equal to V
regulator disabled.”
The sentence originally stated, “V
greater than V
regulator disabled.”
Considerations in Asynchronous
Counter Mode
USB
USB
at all times, even with the
at all times, even with the
DD
must be greater than or
DD
must be
PIC18F2455/2550/4455/4550
4. Module: Master Synchronous Serial Port
5. Module: 10-Bit Analog-to-Digital (A/D)
6. Module: Special Features of the CPU
In Section 19.3.5 “Master Mode,” the second
paragraph of the second column is corrected to
read, “This allows a maximum data rate (at
48 MHz) of 12.00 Mbps.”
The sentence originally stated, “This allows a
maximum data rate (at 48 MHz) of 2.00 Mbps.”
In Register 21-1, the display and the detailed bit
description for bit 5 is corrected to “VCFG1”,
rather than “VCFG0”. All other bit 5 displays and
descriptions are correct in the Device Data Sheet.
In Section 25.9.1 “Dedicated ICD/ICSP Port”,
the second sentence of the fourth paragraph is
corrected to state, “When V
MCLR/V
pin is ignored”. This refers to the high-voltage
programming voltage level for ICSP™ (DC
Specification D110).
The sentence originally stated, “When V
on the MCLR/V
ICV
the maximum input voltage tolerated by the pin as
an I/O (DC specification D040).
PP
pin is ignored”. That incorrectly referred to
PP
(MSSP)
Converter
/RE3 pin, the state of the ICRST/ICV
PP
/RE3 pin, the state of the ICRST/
IHH
DS80478A-page 19
is seen on the
IH
is seen
PP