PIC18LF2480T-I/ML Microchip Technology, PIC18LF2480T-I/ML Datasheet - Page 264
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF2480T-I/ML
Manufacturer Part Number
PIC18LF2480T-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18LF2480-ISP.pdf
(14 pages)
Specifications of PIC18LF2480T-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18LF2480-ISP PDF datasheet #4
- Current page: 264 of 490
- Download datasheet (9Mb)
PIC18F2480/2580/4480/4580
21.1
There are eight modes of operation for the compara-
tors, shown in Figure 21-1. Bits, CM<2:0> of the
CMCON register, are used to select these modes. The
TRISA register controls the data direction of the com-
parator pins for each mode. If the Comparator mode is
FIGURE 21-1:
DS39637D-page 264
Comparators Reset (POR Default Value)
CM<2:0> = 000
Two Independent Comparators
CM<2:0> = 010
Two Common Reference Comparators
CM<2:0> = 100
One Independent Comparator with Output
CM<2:0> = 001
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
A = Analog Input, port reads zeros always
* Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs.
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
RE1/WR/AN6/C1OUT*
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
Comparator Configuration
A
A
A
D
A
A
A
A
A
A
A
A
COMPARATOR I/O OPERATING MODES
A
A
D
D
V
V
V
V
V
V
V
V
V
V
V
V
IN
IN
IN
IN
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN
-
+
-
+
IN
IN
IN
IN
-
+
-
+
-
+
-
+
-
+
-
+
C1
C2
C1
C2
C1
C2
C1
C2
C1OUT
C2OUT
D = Digital Input
Off
(Read as ‘0’)
Off
(Read as ‘0’)
C1OUT
C2OUT
C1OUT
Off
(Read as ‘0’)
Two Common Reference Comparators with Outputs
CM<2:0> = 101
Two Independent Comparators with Outputs
CM<2:0> = 011
Comparators Off
CM<2:0> = 111
Four Inputs Multiplexed to Two Comparators
CM<2:0> = 110
RD1/PSP1/
C1IN-
RD0/PSP0/
C1IN+
RD3/PSP3/
C2IN-
RD2/PSP2/
C2IN+
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
RE1/WR/AN6/C1OUT*
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
RE2/CS/AN7/C2OUT*
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
RE1/WR/AN6/C1OUT*
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
RE2/CS/AN7/C2OUT*
changed, the comparator output level may not be valid
for the specified mode change delay shown in
Section 28.0 “Electrical Characteristics”.
Note:
CIS (CMCON<3>) is the Comparator Input Switch
A
A
A
A
Comparator interrupts should be disabled
during a Comparator mode change;
otherwise, a false interrupt may occur.
CIS = 0
CIS = 1
CIS = 0
CIS = 1
A
A
A
D
A
A
A
A
D
D
D
D
© 2009 Microchip Technology Inc.
V
V
V
V
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
-
+
-
+
-
+
-
+
V
V
V
V
-
+
-
+
IN
IN
IN
IN
CV
-
+
-
+
C1
C2
C1
C2
C1
C2
REF
C1
C2
From V
Off
(Read as ‘0’)
Off
(Read as ‘0’)
C1OUT
C2OUT
C1OUT
C2OUT
REF
C1OUT
C2OUT
Module
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