PIC18F8621-E/PT Microchip Technology, PIC18F8621-E/PT Datasheet - Page 392

• Manufacturer Part Number: PIC18F8621-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8621-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6525/6621/8525/8621
Timing Specifications ........................................................ 337
DS39612B-page 390
Slave Synchronization .............................................. 179
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) .......................................... 178
SPI Mode (Slave Mode with CKE = 0) ...................... 180
SPI Mode (Slave Mode with CKE = 1) ...................... 180
Stop Condition Receive or Transmit Mode ............... 206
Synchronous Reception
Synchronous Transmission....................................... 227
Synchronous Transmission (Through TXEN) ........... 228
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock ........................... 342
Timing for Transition Between Timer1 and
Timing for Transition Between Timer1 and
Transition Between Timer1 and
Transition Between Timer1 and
Transition from OSC1 to Timer1 Oscillator ................. 26
Wake-up from Sleep via Interrupt ............................. 270
A/D Conversion Requirements ................................. 355
Capture/Compare/PWM Requirements .................... 343
CLKO and I/O Requirements .................................... 338
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode
via 1 kΩ Resistor)................................................ 38
(Master Mode, SREN)....................................... 229
(MCLR Tied to V
Not Tied to V
Not Tied to V
Tied to V
OSC1 (EC with PLL Active, SCS1 = 1)............... 27
OSC1 (HS with PLL Active, SCS1 = 1)............... 27
OSC1 (HS, XT, LP)............................................. 26
OSC1 (RC, EC)................................................... 28
Requirements.................................................... 353
Requirements.................................................... 353
(Master Mode, CKE = 0) ................................... 345
(Master Mode, CKE = 1) ................................... 346
(Slave Mode, CKE = 0) ..................................... 347
Requirements (CKE = 1)................................... 348
DD
via 1 kΩ Resistor) ............................ 37
DD
DD
): Case 1 .................................... 37
): Case 2 .................................... 37
DD
via 1 kΩ Resistor) ............... 38
DD
TRISE Register
TSTFSZ ............................................................................ 315
Two-Word Instructions
TXSTAx Register
V
Voltage Reference Specifications..................................... 332
W
Wake-up from Sleep ................................................. 259, 269
Watchdog Timer (WDT)............................................ 259, 267
WCOL ....................................................... 201, 202, 203, 206
WCOL Status Flag.................................... 201, 202, 203, 206
WWW, On-Line Support ....................................................... 5
X
XORLW............................................................................. 315
XORWF ............................................................................ 316
External Clock Requirements ................................... 337
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements............................. 344
PLL Clock ................................................................. 338
Program Memory Read Requirements ..................... 339
Program Memory Write Requirements ..................... 340
Reset, Watchdog Timer, Oscillator
Timer0 and Timer1 External
PSPMODE Bit................................................... 111, 128
Example Cases........................................................... 46
BRGH Bit .................................................................. 217
Using Interrupts ........................................................ 269
Associated Registers ................................................ 268
Control Register........................................................ 267
Postscaler ................................................................. 268
Programming Considerations ................................... 267
RC Oscillator............................................................. 267
Time-out Period ........................................................ 267
2
2
C Bus Data Requirements (Slave Mode) ............... 350
C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 349
Requirements ................................................... 351
Start-up Timer, Power-up Timer
and Brown-out Reset Requirements ................ 341
Clock Requirements ......................................... 342
2
2
C Bus Data Requirements ................. 352
C Bus Start/Stop Bits
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