PIC18F4580-E/PT Microchip Technology, PIC18F4580-E/PT Datasheet - Page 260

• Manufacturer Part Number: PIC18F4580-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
20.4
The selection of the automatic acquisition time and A/D
conversion clock is determined in part, by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in the Sleep mode requires the A/D F
clock to be selected. If bits, ACQT<2:0>, are set to
‘000’ and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
DS39637D-page 260
Operation in Power-Managed
Modes
RC
20.5
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (V
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
2: Analog levels on any pin defined as a
3: The
Configuring Analog Port Pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured
converted.
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
Register 3H configures PORTB pins to
reset as analog or digital pins by control-
ling how the PCFG bits in ADCON1 are
reset.
OH
or V
PBADEN
OL
© 2009 Microchip Technology Inc.
) will be converted.
input
bit
will
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be
Configuration
accurately