PIC18F4455-I/ML Microchip Technology, PIC18F4455-I/ML Datasheet - Page 3
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4455-I/ML
Manufacturer Part Number
PIC18F4455-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
Specifications of PIC18F4455-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
24KB (12K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Details
TABLE 2:
© 2009 Microchip Technology Inc.
BOR
MSSP
MSSP
Timer1/3
BOR
BOR
EUSART
MSSP
MSSP
MSSP
MSSP
EUSART
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
HLVD or USB
I
Eight-Bit
Async
Threshold
Synch
Master
I
I
SPI slave
Threshold
SPI Slave
SPI modes
Interrupts
2
2
2
C mode
C Slave
C Master
Feature
SILICON ISSUE SUMMARY (CONTINUED)
Number
Item
30.
31.
33.
34.
35.
36.
39.
40.
41.
32.
37.
38.
Clearing SBOREN can cause BOR
I
SPI slave not meeting timing parameter 70
Need delay between consecutive writes
Certain conditions move BOR threshold
Table reads can move BOR threshold
Synchronous master mode, DT data changes
SPI Slave needs a series resistor
SPI modes, incoming data not received if BF set
With I
promptly
In I
slave clock stretch
If interrupts are enabled, 2 T
after re-enabling the module
2
C baud rate not meeting formula
2
C Master mode, narrow clock width upon
2
C slave reception, need to read data
PIC18F2455/2550/4455/4550
Issue Summary
CY
delay needed
A3
X
X
X
Affected Revisions
B4
X
X
X
X
X
X
X
X
DS80478A-page 3
B5
X
X
X
X
X
X
X
B6
X
X
X
X
X
X
X
(1)
B7
X
X
X
X
X
X