PIC18F4455-I/ML Microchip Technology, PIC18F4455-I/ML Datasheet - Page 17
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PIC18F4455-I/ML
Manufacturer Part Number
PIC18F4455-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
Specifications of PIC18F4455-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
24KB (12K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Details
39. Module: MSSP (I
EXAMPLE 9:
© 2009 Microchip Technology Inc.
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf
nop
nop
;CPU may now execute 2 cycle instructions
When configured for I
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read after the SSPIF interrupt (PIR1<3>) has
occurred, but before the first rising clock edge of
the next byte being received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Affected Silicon Revisions
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next byte
being received.
A3
X
RCSTA1, SPEN ;or RCSTA2 if EUSART2
;1 Tcy delay
;1 Tcy delay (two total)
is
done
B4
X
2
RE-ENABLING A EUSART MODULE
C slave reception, enable the
2
by
C™ Slave)
2
B5
X
C™ slave reception, the
setting
B6
X
the
SEN
PIC18F2455/2550/4455/4550
B7
X
bit
40. Module: MSSP (I
41. Module: EUSART
When in I
clock stretching, the first clock pulse after the slave
releases the SCL line may be narrower than the
configured clock width. This may result in the slave
missing the first clock in the next transmission/
reception.
Work around
The clock pulse will be the normal width if the slave
does not perform clock stretching.
Affected Silicon Revisions
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
Work around
Add a 2 T
enables the EUSART module (sets SPEN = 1).
See Example 9.
Affected Silicon Revisions
RCSTAx<7> = 0)
after setting SPEN = 1
A3
A3
2
CY
C Master mode, if the slave performs
B4
B4
X
delay after any instruction that re-
2
C™ Master)
B5
B5
X
DS80478A-page 17
B6
B6
X
X
B7
B7
X
X