PIC18F2431T-I/MM Microchip Technology, PIC18F2431T-I/MM Datasheet - Page 16
![16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m T/R](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F2431T-I/MM
Manufacturer Part Number
PIC18F2431T-I/MM
Description
16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18F2431T-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4431 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2431T-I/MM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F2331/2431/4331/4431
TABLE 3-5:
DS30500B-page 16
Step 1: Direct access to config memory.
Step 2: Configure device for single panel writes.
Step 3: Direct access to code memory.
Step 4: Set the table pointer for the block to be erased.
Step 5: Enable memory writes and set up an erase.
Step 6: Perform required sequence.
Step 7: Initiate erase.
Step 8: Wait for P11+P10 and then disable writes.
Step 9: Load write buffer for panel. The correct panel will be selected based on the table pointer.
To continue writing data, repeat step 8, where the Address Pointer is incremented by 8 at each iteration of the loop.
Command
0000
0000
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
4-Bit
8E A6
8C A6
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
8E A6
9C A6
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
84 A6
88 A6
0E 55
6E A7
0E AA
6E A7
82 A6
00 00
94 A6
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MODIFYING CODE MEMORY
Data Payload
BSF
BSF
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
BSF EECON1, EEPGD
BCF EECON1, CFGS
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
BSF EECON1, WREN
BSF EECON1, FREE
MOVLW 55h
MOVWF EECON2
MOVLW 0AAh
MOVWF EECON2
BSF EECON1, WR
NOP
BCF EECON1, WREN
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
EECON1, EEPGD
EECON1, CFGS
Core Instruction
2010 Microchip Technology Inc.