PIC16LF76-I/SS Microchip Technology, PIC16LF76-I/SS Datasheet - Page 73
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PIC16LF76-I/SS
Manufacturer Part Number
PIC16LF76-I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F73-ISP.pdf
(174 pages)
Specifications of PIC16LF76-I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16LF76I/SS
- Current page: 73 of 174
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10.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
TABLE 10-1:
X = value in SPBRG (0 to 255)
TABLE 10-2:
2002 Microchip Technology Inc.
98h
18h
99h
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
Address
SYNC
0
1
USART Baud Rate Generator
(BRG)
TXSTA
RCSTA
SPBRG Baud Rate Generator Register
Name
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
CSRC
SPEN
Bit 7
BRGH = 0 (Low Speed)
Bit 6
RX9
TX9
OSC
SREN CREN
TXEN SYNC
Bit 5
, the nearest
Bit 4
OSC
OSC
/(64(X+1))
/(4(X+1))
Bit 3
—
—
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
10.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
BRGH TRMT TX9D
FERR OERR RX9D
Bit 2
SAMPLING
Bit 1
OSC
/(16(X + 1)) equation can reduce the
Baud Rate = F
BRGH = 1 (High Speed)
Bit 0
PIC16F7X
0000 -010
0000 -00x
0000 0000
Value on:
N/A
POR,
BOR
OSC
DS30325B-page 71
/(16(X+1))
0000 -010
0000 -00x
0000 0000
Value on
RESETS
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