PIC16LC63A-04I/SS Microchip Technology, PIC16LC63A-04I/SS Datasheet - Page 75
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PIC16LC63A-04I/SS
Manufacturer Part Number
PIC16LC63A-04I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC63A-04I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
192 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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TABLE 11-6:
FIGURE 11-8:
0Bh,8Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
RC7/RX/DT pin
RC6/TX/CK pin
Address
2000 Microchip Technology Inc.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.
Write to
bit SREN
SREN bit
CREN bit
RCIF bit
(interrupt)
Read
RXREG
Shaded cells are not used for synchronous master reception.
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'0'
USART Receive register
Baud Rate Generator register
PSPIF
PSPIE
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CSRC
SPEN
Bit 7
GIE
(1)
(1)
ADIE
ADIF
bit0
PEIE
Bit 6
RX9
TX9
(2)
(2)
SREN CREN
TXEN
RCIF
RCIE
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit 5
T0IE
bit1
SYNC
INTE
TXIE
Bit 4
TXIF
bit2
PIC16C63A/65B/73B/74B
SSPIF
SSPIE
RBIE
Bit 3
—
—
bit3
CCP1IE
CCP1IF
BRGH
FERR
Bit 2
T0IF
bit4
TMR2IE TMR1IE 0000 0000
TMR2IF
OERR
TRMT
Bit 1
INTF
bit5
TMR1IF 0000 0000
RX9D
TX9D
RBIF
Bit 0
bit6
0000 000x
0000 -00x
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
bit7
DS30605C-page 75
Q1 Q2 Q3 Q4
0000 000u
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
RESETS
all other
'0'
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