PIC16LC63A-04I/SS Microchip Technology, PIC16LC63A-04I/SS Datasheet - Page 69
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PIC16LC63A-04I/SS
Manufacturer Part Number
PIC16LC63A-04I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC63A-04I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
192 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Steps to follow when setting up an Asynchronous
Transmission:
1.
2.
3.
FIGURE 11-2:
FIGURE 11-3:
TABLE 11-3:
0Bh,8Bh
0Ch
18h
19h
8Ch
98h
99h
Legend: u = unchanged, x = unknown, - = unimplemented locations read as '0'.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
Address
2000 Microchip Technology Inc.
TXIF bit
(interrupt reg. flag)
RC6/TX/CK (pin)
RC6/TX/CK (pin)
TRMT bit
(Transmit shift
reg. empty flag)
Note: This timing diagram shows two consecutive transmissions.
Write to TXREG
Write to TXREG
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT bit
(Transmit shift
reg. empty flag)
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1)
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set interrupt enable bits
TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
BRG output
(shift clock)
BRG output
(shift clock)
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
Shaded cells are not used for asynchronous transmission.
PIR1
RCSTA
TXREG USART Transmit Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
INTCON
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
PSPIF
PSPIE
CSRC
ASYNCHRONOUS MASTER TRANSMISSION
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
SPEN
Bit 7
GIE
Transmit Shift Reg.
Word 1
Word 1
Transmit Shift Reg
Word 1
Word 1
(1)
(1)
ADIE
ADIF
PEIE
Bit 6
RX9
TX9
START Bit
(2)
(2)
START Bit
Word 2
SREN
TXEN
RCIE
RCIF
Bit 5
T0IE
Bit 0
CREN
Bit 0
SYNC
INTE
TXIE
Bit 4
TXIF
PIC16C63A/65B/73B/74B
SSPIE CCP1IE TMR2IE
SSPIF CCP1IF
RBIE
Bit 3
Bit 1
—
—
Word 1
Bit 1
Word 1
4.
5.
6.
7.
BRGH
FERR
Bit 2
T0IF
If 9-bit transmission is desired, then set transmit
bit TX9.
Enable the transmission by setting bit TXEN,
which will also set flag bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts trans-
mission).
TMR2IF
OERR
TRMT
Bit 1
INTF
Bit 7/8
Word 2
Transmit Shift Reg.
Bit 7/8
TMR1IE 0000 0000
TMR1IF 0000 0000
RX9D
TX9D
RBIF
Bit 0
STOP Bit
STOP Bit
0000 -00x
0000 0000
0000 -010
0000 0000
0000 000x
Value on:
POR,
BOR
START Bit
DS30605C-page 69
Word 2
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0000 000u
Value on
RESETS
all other
Bit 0