PIC16F916-E/SO Microchip Technology, PIC16F916-E/SO Datasheet - Page 284
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PIC16F916-E/SO
Manufacturer Part Number
PIC16F916-E/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F913-ISS.pdf
(330 pages)
3.PIC16F913-ISS.pdf
(8 pages)
4.PIC16F913-ISS.pdf
(34 pages)
Specifications of PIC16F916-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
352 B
Interface Type
SSP, I2C, AUSART, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Data Rom Size
256 B
Height
2.31 mm
Length
17.87 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F913-ISS PDF datasheet #2
- PIC16F913-ISS PDF datasheet #3
- PIC16F913-ISS PDF datasheet #4
- Current page: 284 of 330
- Download datasheet (7Mb)
PIC16F913/914/916/917/946
TABLE 19-16: I
DS41250F-page 282
Note 1:
Param.
100*
101*
102*
103*
106*
107*
109*
110*
No.
90*
91*
92*
2:
*
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I
T
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line T
line is released.
T
T
T
T
T
T
T
T
T
T
T
C
SU
SU
SU
SU
AA
R
Symbol
HIGH
LOW
F
HD
HD
BUF
B
:
:
:
:
:
:
DAT
STA
DAT
STO
STA
DAT
R
max. + T
2
≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
C™ BUS DATA REQUIREMENTS
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall time 400 kHz mode
Start condition setup
time
Start condition hold
time
Data input hold time
Data input setup time
Stop condition setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
SU
:
DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus device can be used in a Standard mode (100 kHz) I
Characteristic
400 kHz mode
SSP Module
400 kHz mode
SSP Module
400 kHz mode
400 kHz mode
400 kHz mode
400 kHz mode
400 kHz mode
400 kHz mode
400 kHz mode
400 kHz mode
20 + 0.1C
20 + 0.1C
1.5T
1.5T
Min.
100
0.6
1.3
1.3
0.6
0.6
1.3
—
—
0
CY
CY
B
B
Max.
250
250
0.9
400
—
—
—
—
—
—
—
—
—
—
Units
2
μs
μs
ns
ns
μs
μs
μs
ns
μs
ns
μs
pF
C bus specification), before the SCL
2
C bus system, but the requirement
© 2007 Microchip Technology Inc.
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 10 MHz
C
10-400 pF
C
10-400 pF
Only relevant for Repeated
Start condition
After this period the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
Conditions
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