PIC16F883-E/ML Microchip Technology, PIC16F883-E/ML Datasheet - Page 95
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F883-E/ML
Manufacturer Part Number
PIC16F883-E/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.MCP1631RD-MCC2.pdf
(328 pages)
3.PIC16F882-ISS.pdf
(16 pages)
4.PIC16F882-ISS.pdf
(36 pages)
Specifications of PIC16F883-E/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCP1631RD-MCC2 - REFERENCE DESIGN MCP1631HV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- MCP1631RD-MCC2 PDF datasheet #2
- PIC16F882-ISS PDF datasheet #3
- PIC16F882-ISS PDF datasheet #4
- Current page: 95 of 328
- Download datasheet (6Mb)
REGISTER 8-4:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
SR1
2:
(2)
The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on
the pin), regardless of the SR latch operation.
To enable an SR Latch output to the pin, the appropriate CxOE and TRIS bits must be properly
configured.
SR1: SR Latch Configuration bit
1 =
0 =
SR0: SR Latch Configuration bits
1 =
0 =
C1SEN: C1 Set Enable bit
1 = C1 comparator output sets SR latch
0 = C1 comparator output has no effect on SR latch
C2REN: C2 Reset Enable bit
1 = C2 comparator output resets SR latch
0 = C2 comparator output has no effect on SR latch
PULSS: Pulse the SET Input of the SR Latch bit
1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
PULSR: Pulse the Reset Input of the SR Latch bit
1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
Unimplemented: Read as ‘0’
FVREN: Fixed Voltage Reference Enable bit
1 = 0.6V Reference FROM INTOSC LDO is enabled
0 = 0.6V Reference FROM INTOSC LDO is disabled
SR0
R/W-0
C2OUT pin is the latch Q output
C2OUT pin is the C2 comparator output
C1OUT pin is the latch Q output
C1OUT pin is the C1 Comparator output
SRCON: SR LATCH CONTROL REGISTER
(2)
W = Writable bit
‘1’ = Bit is set
C1SEN
R/W-0
PIC16F882/883/884/886/887
C2REN
(2)
R/W-0
(2)
S = Bit is set only -
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PULSS
R/S-0
PULSR
R/S-0
x = Bit is unknown
U-0
—
DS41291F-page 93
FVREN
R/W-0
bit 0
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