PIC16F872-E/SP Microchip Technology, PIC16F872-E/SP Datasheet - Page 86

• Manufacturer Part Number: PIC16F872-E/SP
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-E/SP

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F872
10.4
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers). After
the A/D conversion is aborted, acquisition on the
selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
FIGURE 10-3:
10.4.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
FIGURE 10-4:
DS30221C-page 84
conversion
A/D Conversions
A/D RESULT REGISTERS
T
CY
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
7
to T
0000 00
ADRESH
AD
Conversion Starts
A/D CONVERSION T
A/D RESULT JUSTIFICATION
T
sample.
AD
Right Justified
1
2 1 0 7
ADFM = 1
T
AD
b9
2
That
10-bit Result
T
ADRESL
AD
b8
3
T
AD
is,
b7
AD
4
0
CYCLES
T
the
AD
b6
10-Bit Result
5
T
AD
b5
6
In Figure 10-3, after the GO bit is set, the first time seg-
ment has a minimum of T
Format Select bit (ADFM) controls this justification.
Figure 10-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
T
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
AD
b4
Note:
7
7
T
AD
b3
ADRESH
8
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
10-bit Result
T
AD
b2
ADFM = 0
9
Left Justified
T
0 7 6 5
AD
b1
10 T
© 2006 Microchip Technology Inc.
CY
ADRESL
and a maximum of T
AD
b0
0000 00
11
0
AD
.