PIC16F872-E/SP Microchip Technology, PIC16F872-E/SP Datasheet - Page 17
PIC16F872-E/SP
Manufacturer Part Number
PIC16F872-E/SP
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F872-ISO.pdf
(168 pages)
5.PIC16F872-ISO.pdf
(5 pages)
6.PIC16F872-ISO.pdf
(6 pages)
Specifications of PIC16F872-E/SP
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F872-ISO PDF datasheet #4
- PIC16F872-ISO PDF datasheet #5
- PIC16F872-ISO PDF datasheet #6
- Current page: 17 of 168
- Download datasheet (3Mb)
2.2.2.4
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
© 2006 Microchip Technology Inc.
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
PIE1 Register
PIE1 REGISTER (ADDRESS: 8Ch)
bit 7
Reserved: Always maintain these bits clear
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
Reserved: Always maintain these bits clear
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
- n = Value at POR
reserved
R/W-0
R/W-0
ADIE
reserved
R/W-0
W = Writable bit
’1’ = Bit is set
reserved
R/W-0
Note:
SSPIE
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
CCP1IE
R/W-0
PIC16F872
x = Bit is unknown
TMR2IE
R/W-0
DS30221C-page 15
TMR1IE
R/W-0
bit 0
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