PIC16F685-I/ML Microchip Technology, PIC16F685-I/ML Datasheet - Page 42
PIC16F685-I/ML
Manufacturer Part Number
PIC16F685-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
Specifications of PIC16F685-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINDVA1004 - DEVICE ADAPTER 8/14/20DIP
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- Current page: 42 of 306
- Download datasheet (6Mb)
PIC16F631/677/685/687/689/690
2.2.2.5
The PIE2 register contains the interrupt enable bits, as
shown in Register 2-5.
REGISTER 2-5:
DS41262E-page 40
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
OSFIE
R/W-0
PIE2 Register
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables oscillator fail interrupt
0 = Disables oscillator fail interrupt
C2IE: Comparator C2 Interrupt Enable bit
1 = Enables Comparator C2 interrupt
0 = Disables Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables Comparator C1 interrupt
0 = Disables Comparator C1 interrupt
EEIE: EE Write Operation Interrupt Enable bit
1 = Enables write operation interrupt
0 = Disables write operation interrupt
Unimplemented: Read as ‘0’
R/W-0
C2IE
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
C1IE
R/W-0
EEIE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
U-0
—
© 2008 Microchip Technology Inc.
x = Bit is unknown
U-0
—
U-0
—
bit 0
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