PIC16C712-04/SO Microchip Technology, PIC16C712-04/SO Datasheet - Page 65

• Manufacturer Part Number: PIC16C712-04/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,18PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C712-04/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 4 bit
• Data Rom Size: 128 B
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

9.12
The Watchdog Timer is as a free running, on-chip, RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device have been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT Time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT Time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer Time-out.
The WDT can be permanently disabled by clearing
Configuration bit WDTE (Section 9.1 “Configuration
Bits”).
FIGURE 9-15:
FIGURE 9-16:
© 2005 Microchip Technology Inc.
Address Name
2007h
81h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 9-1 for operation of these bits.
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
Watchdog Timer (WDT)
Config. bits
OPTION_REG
WATCHDOG TIMER BLOCK DIAGRAM
SUMMARY OF WATCHDOG TIMER REGISTERS
WDT Timer
Enable Bit
WDT
Bits 13:8
N/A
(1)
From TMR0 Clock Source
(Figure 4-2)
RBPU
Bit 7
—
0
1
PSA
BODEN
M
U
X
INTEDG
Bit 6
(1)
T0CS T0SE
Bit 5
CP1
WDT time-out period values may be found in the
Electrical Specifications section under T
ter #31). Values for the WDT prescaler (actually a
postscaler, but shared with the Timer0 prescaler) may
be assigned using the OPTION_REG register.
.
0
Note:
Note:
Time-out
8-to-1 MUX
MUX
WDT
Postscaler
Bit 4
CP0
1
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out
and generating a device Reset condition.
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
8
PWRTE
PIC16C712/716
Bit 3
PSA
PSA
To TMR0 (Figure 4-2)
(1)
PS2:PS0
WDTE FOSC1 FOSC0
Bit 2
PS2
DS41106B-page 63
Bit 1
PS1
WDT
(parame-
Bit 0
PS0