PIC16C712-04/SO Microchip Technology, PIC16C712-04/SO Datasheet
PIC16C712-04/SO
Specifications of PIC16C712-04/SO
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PIC16C712-04/SO Summary of contents
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... CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM © 2005 Microchip Technology Inc. PIC16C712/716 Data Sheet DS41106B ...
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... PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM Devices included in this Data Sheet: • PIC16C712 • PIC16C716 Microcontroller Core Features: • High-performance RISC CPU • Only 35 single-word instructions to learn • All single-cycle instructions except for program branches which are two cycle • ...
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... In-Circuit Serial Yes Features Programming™ Brown-out Reset Yes Packages 18-pin DIP, SOIC; 20-pin SSOP DS41106B-page 2 PIC16C712 DC – 20 MHz POR, BOR (PWRT, OST) 1K 128 7 Ports A input channels PIC16C71 PIC16C711 PIC16C712 PIC16C715 128 128 TMR0 TMR0 TMR0 TMR0 TMR1 TMR2 — — 1 — ...
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... Index ................................................................................................................................................................................................... 97 On-Line Support................................................................................................................................................................................. 101 Reader Response .............................................................................................................................................................................. 102 PIC16C712/716 Product Identification System .................................................................................................................................. 103 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced ...
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... PIC16C712/716 NOTES: DS41106B-page 4 © 2005 Microchip Technology Inc. ...
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... Timer1 CCP1 Note 1: Higher order bits are from the STATUS register. © 2005 Microchip Technology Inc. There are two devices (PIC16C712, PIC16C716) covered by this data sheet. Figure 1-1 is the block diagram for both devices. The ® pinouts are listed in Table 1-1. ...
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... PIC16C712/716 TABLE 1-1: PIC16C712/716 PINOUT DESCRIPTION Pin PIC16C712/716 Name DIP, SOIC SSOP MCLR MCLR V PP OSC1/CLKIN 16 OSC1 CLKIN OSC2/CLKOUT 15 OSC2 CLKOUT RA0/AN0 17 RA0 AN0 RA1/AN1 18 RA1 AN1 RA2/AN2 1 RA2 AN2 RA3/AN3/V 2 REF RA3 AN3 V REF RA4/T0CKI 3 RA4 T0CKI Legend: TTL = TTL-compatible input ...
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... TABLE 1-1: PIC16C712/716 PINOUT DESCRIPTION (CONTINUED) Pin PIC16C712/716 Name DIP, SOIC SSOP RB0/INT 6 RB0 INT RB1/T1OSO/T1CKI 7 RB1 T1OSO T1CKI RB2/T1OSI 8 RB2 T1OSI RB3/CCP1 9 RB3 CCP1 RB4 10 RB5 11 RB6 12 RB7 15 Legend: TTL = TTL-compatible input ST = Schmitt Trigger input with CMOS levels OD = Open drain output SM = SMBus compatible input ...
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... PIC16C712/716 NOTES: DS41106B-page 8 © 2005 Microchip Technology Inc. ...
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... Program Memory Organization The PIC16C712/716 has a 13-bit Program Counter (PC) capable of addressing program mem- ory space. PIC16C712 has words of program memory and PIC16C716 has words of program memory. Accessing a location above the physically implemented address will cause a wraparound. The Reset vector is at 0000h and the interrupt vector is at 0004h ...
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... PIC16C712/716 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. (1) RP0 (STATUS<6:5>) RP1 = 00 Bank Bank Bank 2 (not implemented Bank 3 (not implemented) ...
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... This is the value that will be in the port output latch. 7: Reserved bits; Do Not Use. © 2005 Microchip Technology Inc. PIC16C712/716 The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section ...
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... PIC16C712/716 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Addr Name Bit 7 Bit 6 Bank 1 (1) 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) OPTION_ 81h RBPU INTEDG REG (1) 82h PCL Program Counter’s (PC) Least Significant Byte ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. © 2005 Microchip Technology Inc. PIC16C712/716 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the bits from the STATUS register ...
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... PIC16C712/716 2.2.2.2 OPTION_REG Register The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assign- able register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. FIGURE 2-5: ...
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... RBIF: RB Port Change Interrupt Flag bit least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state © 2005 Microchip Technology Inc. PIC16C712/716 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... PIC16C712/716 2.2.2.4 PIE1 Register This register contains the individual enable bits for the peripheral interrupts. FIGURE 2-7: PIE1 REGISTER (ADDRESS 8Ch) U-0 R/W-0 U-0 U-0 — ADIE — — bit7 bit 7: Unimplemented: Read as ‘0’ bit 6: ADIE: A/D Converter Interrupt Enable bit ...
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... TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow © 2005 Microchip Technology Inc. PIC16C712/716 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... PIC16C712/716 2.2.2.6 PCON Register The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR external MCLR Reset or WDT Reset. These devices contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. FIGURE 2-9: PCON REGISTER (ADDRESS 8Eh) ...
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... The tenth push overwrites the second push (and so on). © 2005 Microchip Technology Inc. PIC16C712/716 2.4 Program Memory Paging The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page ...
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... DS41106B-page 20 EXAMPLE 2-2: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE : An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-10. However, IRP is not used in the PIC16C712/716. 0 IRP (2) bank select 80h 100h 180h (3) (3) ...
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... Microchip Technology Inc. PIC16C712/716 Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. ...
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... PIC16C712/716 FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 DATA BUS WR PORT WR TRIS RD PORT To A/D Converter FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN DATA BUS WR PORT WR TRIS RD PORT TMR0 Clock Input DS41106B-page Data Latch Analog input TRIS Latch mode RD TRIS I/O Pin N Data Latch Schmitt ...
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... Input/output or external clock input for Timer0 Output is open drain type Bit 2 Bit 1 (1) RA4 RA3 RA2 RA1 (1) PORTA Data Direction Register — — — PCFG2 PCFG1 PCFG0 PIC16C712/716 Value on Value on all Bit 0 POR, other Resets BOR RA0 --xx xxxx --xu uuuu --11 1111 --11 1111 ---- -000 ---- -000 DS41106B-page 23 ...
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... PIC16C712/716 3.2 PORTB and the TRISB Register PORTB is an 8-bit wide bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input, (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output, (i ...
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... The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. (1) RBPU T1OSCEN T1CS TTL Buffer 0 T1CLKIN ST Buffer PIC16C712/716 Weak V DD Pull-up RB1/T1OSO/T1CKI V SS DS41106B-page 25 ...
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... PIC16C712/716 FIGURE 3-5: BLOCK DIAGRAM OF RB2/T1OSI PIN (1) RBPU T1OSCEN PORTB<2> DATA BUS PORTB CK Q TRISB<2> TRISB CK Q T1OSCEN RD PORTB Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). FIGURE 3-6: BLOCK DIAGRAM OF RB3/CCP1 PIN ...
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... TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or peripheral input. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. © 2005 Microchip Technology Inc. PIC16C712/716 V DD weak P ...
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... PIC16C712/716 TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 06h PORTB RB7 RB6 86h TRISB PORTB Data Direction Register 81h OPTION_REG RBPU INTEDG Legend unknown unchanged. Shaded cells are not used by PORTB. DS41106B-page 28 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...
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... Timer0 will clear the prescaler count, but will not change the prescaler assignment. PSout 1 Sync with Internal clocks Programmable 0 (2) Prescaler (2-cycle delay) 3 (1) (1) PS2, PS1, PS0 PSA PIC16C712/716 ® Mid-Range Reference Data Bus 8 TMR0 PSout Set Interrupt Flag bit T0IF on overflow DS41106B-page 29 ...
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... PIC16C712/716 4.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). Note: To avoid an unintended device Reset, a specific instruction sequence (shown in ® the PICmicro Mid-Range Reference Manual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT ...
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... Internal clock (F /4) OSC bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2005 Microchip Technology Inc. PIC16C712/716 5.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON< ...
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... PIC16C712/716 FIGURE 5-2: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1 TMR1H T1OSC RB1/T1OSO/T1CKI RB2/T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 5.2 Timer1 Module and PORTB Operation When Timer1 is configured as timer running from the main oscillator, PORTB< ...
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... Counter External circuit T1CON = --xx 0x11 TR1SCCP = ---- -x-1 Firmware T1CON = --xx 0x11 TR1SCCP = ---- -x-0 Timer1 oscillator T1CON = --xx 1x11 © 2005 Microchip Technology Inc. PIC16C712/716 TMR1 Module Operation PORTB<2:1> Operation Off PORTB<2:1> function as normal I/O TMR1 module uses the main PORTB<2:1> function as normal oscillator as clock source. ...
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... PIC16C712/716 5.3 Timer1 Oscillator A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output enabled by setting control bit T1OSCEN (T1CON<3>). The oscilla- tor is a low-power oscillator rated up to 200 kHz. It will continue to run during Sleep primarily intended for a 32 kHz crystal. Table 5-2 shows the capacitor selection for the Timer1 oscillator ...
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... NOTES: © 2005 Microchip Technology Inc. PIC16C712/716 DS41106B-page 35 ...
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... PIC16C712/716 6.0 TIMER2 MODULE The Timer2 module timer has the following features: • 8-bit timer (TMR2 register) • 8-bit period register (PR2) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • ...
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... Bit 3 Bit 2 T0IE INTE RBIE T0IF — — — CCP1IF TMR2IF — — — CCP1IE TMR2IE PIC16C712/716 Value on Value on Bit 1 Bit 0 POR, all other BOR Resets 0000 000x 0000 000u INTF RBIF -00- -000 0000 -000 TMR1IF -0-- -000 0000 -000 TMR1IE 0000 0000 0000 0000 ...
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... PIC16C712/716 NOTES: DS41106B-page 38 © 2005 Microchip Technology Inc. ...
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... R/W-0 R/W-0 R/W-0 R/W-0 CCP1M2 CCP1M1 CCP1M0 R/W-1 R/W-1 R/W-1 R/W-1 — TCCP — TT1CK PIC16C712/716 ® Mid-Range Reference Manual, CCP MODE – TIMER RESOURCE Timer Resource Timer1 Timer1 Timer2 R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR Reset ...
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... PIC16C712/716 7.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1. An event is defined as: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON< ...
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... CCP1IF TMR2IF DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 — — — TCCP — — — CCP1IE TMR2IE PIC16C712/716 Value on Value on Bit 1 Bit 0 POR, all other BOR Resets — DT1CK xxxx xxxx xxxx xuxu INTF RBIF 0000 000x 0000 000u ...
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... PIC16C712/716 7.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISCCP<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
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... PR2 Timer2 Module’s Period Register Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2. © 2005 Microchip Technology Inc. PIC16C712/716 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz ...
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... PIC16C712/716 7.4 CCP1 Module and PORTB Operation When the CCP module is disabled, PORTB<3> operates as a normal I/O pin. When the CCP module is enabled, PORTB<3> operation Multiplexing details of the CCP1 module are shown on PORTB<3>, refer to Figure 3.6. Table 7-5 below shows the effects of the CCP module operation on PORTB< ...
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... Figure 8-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference digital I/O. R/W-0 R/W-0 U-0 CHS0 GO/DONE — PIC16C712/716 ® Mid-Range Reference Manual, R/W-0 ADON R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘ ...
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... PIC16C712/716 FIGURE 8-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 — — — — bit7 bit 7-3: Unimplemented: Read as ‘0’ bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 A 0x0 A 0x1 A 100 A 101 D 11x A = Analog input D = Digital I/O ...
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... A/D Converter V REF (Reference voltage) © 2005 Microchip Technology Inc. PIC16C712/716 1. Configure the A/D module: • Configure analog pins/voltage reference/ and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) 2 ...
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... PIC16C712/716 8.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the Charge Holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 8-4. The source impedance (R ) and the internal sampling switch (R ...
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... Device Frequency 20 MHz 5 MHz (2) (2) 100 ns 400 ns (2) 1.6 s 400 ns 1.6 s 6.4 s (1,4) (1,4) 2-6 s 2-6 s time time. AD PIC16C712/716 will be converted 1.25 MHz 333.33 kHz 1 6 (3) (3) 25 (1,4) (1) 2-6 s 2-6 s DS41106B-page 49 ...
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... PIC16C712/716 8.4 A/D Conversions Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. 8.5 Use of the CCP Trigger An A/D conversion can be started by the “Special Event Trigger” of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON< ...
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... SPECIAL FEATURES OF THE CPU The PIC16C712/716 devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection. These are: • OSC Selection • Reset: - Power-on Reset (POR) - Power-up Timer (PWRT) ...
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... Code Protection for 2K Program memory (PIC16C716 Programming code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFh code protected bit 13-8, 5-4: Code Protection for 1K Program memory bits (PIC16C712 Programming code protection off 10 = Programming code protection off 01 = 0200h-03FFh code-protected 00 = 0000h-03FFh code-protected bit 7: Unimplemented: Read as ‘ ...
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... Table 9-2 for nents may be required in HS mode, as well as XT mode to avoid overdriving crystals with low drive level specification. PIC16C712/716 CERAMIC RESONATORS Freq OSC1 OSC2 68-100 pF 68-100 pF 15-68 pF 15-68 pF 15-68 pF ...
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... PIC16C712/716 9.2.3 RC OSCILLATOR For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resis- tor (R ) and capacitor (C ) values and the operat- EXT EXT ing temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal pro- cess parameter variation ...
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... The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from Sleep. 9.7 Brown-Out Reset (BOR) The PIC16C712/716 members have on-chip Brown- out Reset circuitry. A Configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry ...
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... PIC16C712/716 FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR SLEEP WDT WDT Module Time-out Reset V rise DD detect Power-on Reset V DD Brown-out Reset BODEN OST/PWRT OST 10-bit Ripple counter OSC1 (1) PWRT On-chip 10-bit Ripple counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. ...
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... DD such that 0. Internal Brown-out Reset should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. © 2005 Microchip Technology Inc. PIC16C712/716 FIGURE 9-10: EXTERNAL BROWN-OUT PROTECTION CIRCUIT MCP809 V DD bypass capacitor Vss V DD RST ...
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... PIC16C712/716 9.9 Power Control/Status Register (PCON) The Power Control/Status Register, PCON has two bits. Bit 0 is Brown-out Reset Status bit, BOR. If the BODEN Configuration bit is set, BOR is ‘1’ on Power-on Reset. If the BODEN Configuration bit is clear, BOR is unknown on Power-on Reset. TABLE 9-3: ...
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... TABLE 9-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16C712/716 Register Power-on Reset, Brown-out Reset W xxxx xxxx INDF N/A TMR0 xxxx xxxx PCL 0000h STATUS 0001 1xxx FSR xxxx xxxx (4) --0x 0000 PORTA (5) xxxx xxxx PORTB DATACCP ---- -x-x PCLATH ---0 0000 INTCON 0000 -00x ...
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... PIC16C712/716 FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 9-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 9-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... Interrupts The PIC16C712/716 devices have sources of interrupt. The Interrupt Control Register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the GIE bit. ...
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... PIC16C712/716 9.10.1 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered, either rising if bit INTEDG (OPTION_REG<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt ...
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... Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 9-1 for operation of these bits. © 2005 Microchip Technology Inc. PIC16C712/716 WDT time-out period values may be found in the Electrical Specifications section under T ter #31). Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register ...
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... PIC16C712/716 9.13 Power-down Mode (Sleep) Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or high-impedance) ...
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... Note: Microchip does not recommend code protecting windowed devices. © 2005 Microchip Technology Inc. PIC16C712/716 postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. • If the interrupt occurs during or after the execu- tion of a SLEEP instruction, the device will imme- diately wake-up from Sleep ...
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... PIC16C712/716 9.16 In-Circuit Serial Programming PIC16CXXX microcontrollers can programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product ...
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... Byte-oriented operations • Bit-oriented operations • Literal and control operations © 2005 Microchip Technology Inc. PIC16C712/716 All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP ...
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... PIC16C712/716 TABLE 10-2: PIC16CXXX INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
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... Plus Development Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2005 Microchip Technology Inc. PIC16C712/716 11.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... PIC16C712/716 11.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
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... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2005 Microchip Technology Inc. PIC16C712/716 11.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...
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... PIC16C712/716 11.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PICmicro devices in DIP packages pins. ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. © 2005 Microchip Technology Inc. (except V , MCLR, and RA4) ......................................... -0. (Note 2) ......................................................................................... 0V to +13.25V ) DD > ∑ pin, inducing currents greater than 80 mA, may cause latch-up PIC16C712/716 + 0.3V ∑ {( ∑( pin rather PP DS41106B-page 73 ) ...
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... PIC16C712/716 FIGURE 12-1: PIC16C712/716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +125°C 6.0 5.5 5.0 4 (Volts) 4.0 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 12-2: PIC16LC712/716 VOLTAGE-FREQUENCY GRAPH, 0°C < TA < +70°C 6.0 5.5 5.0 4 ...
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... DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param Sym. Characteristic No. D001 V Supply Voltage DD D001A D002 RAM Data Retention Voltage D003 V V Start Voltage to ensure inter- POR DD nal Power-on Reset signal D004 Rise Rate to ensure internal VDD DD D004A* ...
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... PIC16C712/716 12.2 DC Characteristics: PIC16LC712/716-04 (Commercial, Industrial) DC CHARACTERISTICS Param Sym. Characteristic No. D001 V Supply Voltage DD D002 RAM Data Retention Voltage D003 V V Start Voltage to ensure inter- POR DD nal Power-on Reset signal D004 Rise Rate to ensure internal VDD DD D004A* Power-on Reset signal D005 V Brown-out Reset ...
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... DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712716-20 (Commercial, Industrial, Extended) PIC16LC712/716-04 (Commercial, Industrial) DC CHARACTERISTICS Param Sym. Characteristic No. Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP ...
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... Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C -40°C -40°C Operating voltage V range as described in DC spec Section 12.1 DD “DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended)” and Section 12.2 “DC Characteristics: PIC16LC712/ 716-04 (Commercial, Industrial)” Min. Typ† Max. Units ...
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... Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low © 2005 Microchip Technology Inc. PIC16C712/716 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance DS41106B-page 79 ...
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... TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature AC CHARACTERISTICS Operating voltage V PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended)” and Section 12.2 “DC Characteristics: PIC16LC712/716-04 (Com- mercial, Industrial)”. LC parts operate for commercial/industrial temp’s only. FIGURE 12-3: ...
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... All specified values are PIC16C712/716 Units Conditions MHz RC and XT osc modes MHz HS osc mode (-04) MHz HS osc mode (-20) kHz LP osc mode MHz RC osc mode ...
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... PIC16C712/716 FIGURE 12-5: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O Pin (input) I/O Pin old value (output) Note: Refer to Figure 12-3 for load conditions. TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym. Characteristic No. 10* TosH2ckL OSC1 to CLKOUT 11* TosH2ckH OSC1¦ to CLKOUT¦ ...
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... Brown-out Reset Pulse Width BOR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2005 Microchip Technology Inc. PIC16C712/716 Min. ...
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... PIC16C712/716 FIGURE 12-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1OSO/T1CKI TMR0 or TMR1 Note: Refer to Figure 12-3 for load conditions. TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym. Characteristic No. 40* Tt0H T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse Width ...
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... TccF CCP1 output fall time * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2005 Microchip Technology Inc. PIC16C712/716 Min Typ† ...
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... PIC16C712/716 TABLE 12-7: A/D CONVERTER CHARACTERISTICS: PIC16C712/716-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C712/716-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC712/716-04 (COMMERCIAL, INDUSTRIAL) Param Sym. Characteristic No. A01 N Resolution R A02 E Total Absolute error ABS A03 E Integral linearity error IL A04 E Differential linearity error DL A05 E Full scale error FS A06 E Offset error ...
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... T /2 § — OSC 1.5 § — — cycle. CY PIC16C712/716 1 Tcy 1 0 NEW_DATA DONE Units Conditions s T based, V 3.0V OSC REF s T based, V full range OSC REF s A/D RC Mode s A/D RC Mode ...
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... PIC16C712/716 NOTES: DS41106B-page 88 © 2005 Microchip Technology Inc. ...
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... For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2005 Microchip Technology Inc. Example PIC16C716-04/P Example XXXXXXXX XXXXXXXX YYWWNNN Example PIC16C712-20 /SO 0510017 Example PIC16C712 -20I/SS 0510017 PIC16C712/716 0510017 PIC16C 716/JW 0510017 DS41106B-page 89 ...
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... PIC16C712/716 13.2 Package Details The following sections give the technical details of the packages. 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width ...
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... L .016 .033 .050 .009 .011 .012 B .014 .017 .020 PIC16C712/716 A2 MILLIMETERS MIN NOM MAX 18 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.39 7.49 7.59 11.33 11.53 11.73 0.25 0.50 ...
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... PIC16C712/716 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 © 2005 Microchip Technology Inc. PIC16C712/716 Units INCHES* ...
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... PIC16C712/716 NOTES: DS41106B-page 94 © 2005 Microchip Technology Inc. ...
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... Reset (and wake-up) types are recognized. Registers are reset differently. 10. Wake-up from Sleep through interrupt is added. © 2005 Microchip Technology Inc. PIC16C712/716 11. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unneces- sary delays on power-up and wake-up ...
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... PIC16C712/716 NOTES: DS41106B-page 96 © 2005 Microchip Technology Inc. ...
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... ADON Bit ................................................................... 45 CHS2:CHS0 Bits........................................................ 45 GO/DONE Bit....................................................... 45, 47 ADCON1 Register .................................................. 12, 45, 46 PCFG2:PCFG0 Bits ................................................... 46 ADRES Register .................................................... 11, 45, 47 Analog-to-Digital Converter. See A/D Architecture PIC16C712/716 Block Diagram ................................... 5 Assembler MPASM Assembler.................................................... 70 B Banking, Data Memory ................................................ 10, 13 BOR. See Brown-out Reset Brown-Out Reset (BOR) .................................................... 55 Brown-out Reset (BOR) ................................... 51, 54, 58, 59 BOR Enable (BODEN Bit) ...
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... RB2.............................................................................. 7 RB3.............................................................................. 7 RB4.............................................................................. 7 RB5.............................................................................. 7 RB6.............................................................................. 7 RB7.............................................................................. 7 V .............................................................................. .............................................................................. 7 SS Pinout Descriptions PIC16C712/716 Pinout Description ............................. 6 PIR1 Register .............................................................. 11, 17 ADIF Bit ..................................................................... 17 CCP1IF Bit................................................................. 17 TMR1IF Bit................................................................. 17 TMR2IF Bit ................................................................. 17 Pointer, FSR ...................................................................... 20 POR. See Power-on Reset PORTA Initialization ................................................................ 21 PORTA Register .................................................. 11, 21 RA3:RA0 Port Pins .................................................... 21 RA4/T0CKI Pin .......................................................... 22 TRISA Register.................................................... 12, 21 PORTB Block Diagram of RB1/T1OSO/T1CKI Pin ...
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... Register File ....................................................................... 10 Register File Map ............................................................... 10 Reset ............................................................................ 51, 54 Block Diagram............................................................ 56 © 2005 Microchip Technology Inc. PIC16C712/716 Brown-out Reset (BOR). See Brown-out Reset (BOR) MCLR Reset. See MCLR Power-on Reset (POR). See Power-on Reset (POR) Reset Conditions for All Registers............................. 59 Reset Conditions for PCON Register ........................ 58 Reset Conditions for Program Counter ...
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... PIC16C712/716 TMR1L Register ................................................... 11, 31 Timer2 Block Diagram............................................................ 36 Postscaler. See Postscaler, Timer2 PR2 Register .................................................. 12, 36, 42 Prescaler. See Prescaler, Timer2 T2CON Register .................................................. 11, 36 TMR2 Register ..................................................... 11, 36 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16 TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 17 TMR2 to PR2 Match Interrupt ........................ 36, 37, 42 Timing Diagrams Time-out Sequence on Power-up ...
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... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC16C712/716 should contact their distributor, DS41106B-page 101 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16C712/716 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... PIC16C716 – 04/P 301 = Commercial temp., V PDIP package, 4 MHz, normal limits, QTP DD pattern #301. PIC16LC712 – 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended V limits. DD PIC16C712 – 20I/P = Industrial temp., PDIP package, 20MHz, normal V limits CMOS LC = Low Power CMOS tape and reel – SOIC, SSOP packages only ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2005 Microchip Technology Inc. EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...