PIC16C712-04/SO Microchip Technology, PIC16C712-04/SO Datasheet - Page 4

• Manufacturer Part Number: PIC16C712-04/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,18PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C712-04/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 4 bit
• Data Rom Size: 128 B
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16C712/716
Code Example 2B:
;***********************************************************************
;
;
;
;
;
;
;
;
Assembly Code To Stop CCP Mode Once Started:
CCP1CONSAV equ 0X??
CCPstop
Assembly Code To Start CCP Mode Once Stopped:
CCPstart
DS80072D-page 4
Call these routines to turn the CCP Mode off or on and ensure RB3 is a known
CCPstop - First sets RB3 to an Input or an Output. If RB3 is an Output then it’s state
CCPstart
Input or Output value when CCP Mode is off.
is made either High or Low. The CCP is then Disabled.
bsf
bcf
bcf
bcf
movf
movwf
movlw
movwf
return
bcf
movf
movwf
return
VALUE FOR CCP1CON.
- Enable CCP Mode. IT IS THE RESPONSIBILITY OF THE USER TO DETERMINE THE CORRECT
STATUS,RP0
TRISB,3
STATUS,RP0
PORTB,3
CCP1CON,W
CCP1CONSAV
0x30
CCP1CON
STATUS,RP0
CCP1CONSAV,W
CCP1CON
; USER IS RESPONSIBLE FOR SUPPLYING RAM MEMORY SPACE
; TO SAVE CCP2CON VALUE.
; Select Bank 1
; RB3 as an Output - set bit TRISB, 3 when RB3
; as an Input is desired.
; Select Bank 0
; RB3 as a Low Level Output - set bit PORTB,3
; for RB3 to be a High Level
; Output.
; Move CCP1CON to ‘W’ register
; Save CCP1CON register value
; Load CCP1CON value in Working register
; Turn Off CCP1CON all Modes
; Select Bank 0
; Move CCP1CONSAV value to ‘W’ register
; Restore CCP1CON to desired Mode of operation.
 2003 Microchip Technology Inc.