PIC12F508T-I/MC Microchip Technology, PIC12F508T-I/MC Datasheet - Page 59
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PIC12F508T-I/MC
Manufacturer Part Number
PIC12F508T-I/MC
Description
768 B Flash, 25 RAM, 6 I/O 8 DFN 2X3mm T/R
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F509T-ISN.pdf
(110 pages)
2.PIC12F509T-ISN.pdf
(4 pages)
3.PIC12F509T-ISN.pdf
(20 pages)
Specifications of PIC12F508T-I/MC
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
768B (512 x 12)
Program Memory Type
FLASH
Ram Size
25 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164334 - MODULE SOCKET FOR 8L 2X3MM DFNAC162059 - HEADER INTRFC MPLAB ICD2 8/14PINDVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICE
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F508T-I/MC
Manufacturer:
TRIQUINT
Quantity:
187
ADDWF
Syntax:
Operands:
Operation:
Status Affected: C, DC, Z
Description:
ANDLW
Description:
ANDWF
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
© 2009 Microchip Technology Inc.
Status Affected: Z
Operands:
Operation:
Syntax:
Add W and f
[ label ] ADDWF
0 ≤ f ≤ 31
d ∈ [0,1]
(W) + (f) → (dest)
Add the contents of the W register
and register ‘f’. If ‘d’ is’0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
AND W with f
[ label ] ANDWF
0 ≤ f ≤ 31
d ∈ [0,1]
(W) .AND. (f) → (dest)
The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
AND literal with W
[ label ] ANDLW
0 ≤ k ≤ 255
(W).AND. (k) → (W)
The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
f,d
f,d
k
PIC12F508/509/16F505
BCF
Syntax:
Operands:
Operation:
Status Affected: None
Description:
BSF
Syntax:
Operands:
Operation:
Status Affected: None
BTFSC
Syntax:
Operands:
Operation:
Status Affected: None
Description:
Description: Bit ‘b’ in register ‘f’ is set.
Bit Clear f
[ label ] BCF
0 ≤ f ≤ 31
0 ≤ b ≤ 7
0 → (f<b>)
Bit ‘b’ in register ‘f’ is cleared.
Bit Set f
[ label ] BSF
0 ≤ f ≤ 31
0 ≤ b ≤ 7
1 → (f<b>)
Bit Test f, Skip if Clear
[ label ] BTFSC f,b
0 ≤ f ≤ 31
0 ≤ b ≤ 7
skip if (f<b>) = 0
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a two-cycle instruction.
f,b
f,b
DS41236E-page 59