PIC12C671-04E/SM Microchip Technology, PIC12C671-04E/SM Datasheet - Page 325
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PIC12C671-04E/SM
Manufacturer Part Number
PIC12C671-04E/SM
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,8PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C671-04E/SM
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Package
8SOIJ
Device Core
PIC
Family Name
PIC12
Maximum Speed
4 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
5
On-chip Adc
4-chx8-bit
Number Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12C671-04E/SM
Manufacturer:
MICROCHIR
Quantity:
20 000
- Current page: 325 of 688
- Download datasheet (3Mb)
17.4.18
1997 Microchip Technology Inc.
SDA
SCL
BCLIF
Multi -Master Communication, Bus Collision, and Bus Arbitration
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data
bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA by letting
SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be
stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus
collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset
the I
If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF
flag is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When
the user services the bus collision interrupt service routine, and if the I
can resume communication by asserting a START condition.
If a START, Repeated Start, STOP, or Acknowledge condition was in progress when the bus col-
lision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respec-
tive control bits in the SSPCON2 register are cleared. When the user services the bus collision
interrupt service routine, and if the I
ing a START condition.
The Master will continue to monitor the SDA and SCL pins, and if a STOP condition occurs, the
SSPIF bit will be set.
A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where
the transmitter left off when bus collision occurred.
In multi-master mode, the interrupt generation on the detection of start and stop conditions allows
the determination of when the bus is free. Control of the I
set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared.
Figure 17-34: Bus Collision Timing for Transmit and Acknowledge
2
C port to its IDLE state.
Data changes
while SCL = 0
SDA released
by master
Preliminary
(Figure
SDA line pulled low
by another source
2
C bus is free, the user can resume communication by assert-
17-34).
Section 17. MSSP
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
2
C bus can be taken when the P bit is
Set bus collision
interrupt (BCLIF).
2
C bus is free, the user
DS31017A-page 17-49
17
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