PIC12C671-04E/SM Microchip Technology, PIC12C671-04E/SM Datasheet - Page 265

• Manufacturer Part Number: PIC12C671-04E/SM
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,8PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C671-04E/SM

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Package: 8SOIJ
• Device Core: PIC
• Family Name: PIC12
• Maximum Speed: 4 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 5
• On-chip Adc: 4-chx8-bit
• Number Of Timers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.4
1997 Microchip Technology Inc.
SSP I
2
C Operation
The SSP module in I
and provides interrupts on start and stop bits in hardware to facilitate software implementations
of the master functions. The SSP module implements the standard and fast mode specifications
as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin,
which is the data. The user must configure these pins as inputs through the TRIS bits. The SSP
module functions are enabled by setting SSP Enable bit, SSPEN (SSPCON<5>).
A “glitch” filter is on the SCL and SDA pins when the pin is an input. This filter operates in both
the 100 KHz and 400 KHz modes. In the 100 KHz mode, when these pins are an output, there
is a slew rate control of the pin that is independent of device frequency.
Figure 16-7: SSP Block Diagram (I
2
C mode fully implements all slave functions, except General Call Support,
SCL
SDA
Read
clock
shift
2
Appendix A
C Mode)
MSb
Stop bit detect
Match detect
SSPADD reg
SSPBUF reg
SSPSR reg
Start and
Section 16. BSSP
gives an overview of the I
LSb
Write
(SSPSTAT reg)
data bus
Internal
Set, Reset
S, P bits
Addr Match
2
DS31016A-page 16-15
C bus specification.
16