LMH6702MA National Semiconductor, LMH6702MA Datasheet - Page 9

• Manufacturer Part Number: LMH6702MA
• Description: Operational Amplifier (Op-Amp) IC
• Manufacturer: National Semiconductor

Specifications of LMH6702MA

• Op Amp Type: Low Distortion
• No. Of Amplifiers: 1
• Bandwidth: 720MHz
• Slew Rate: 3100V/µs
• Supply Voltage Range: ± 5V To ± 6V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Number Of Channels: 1
• Common Mode Rejection Ratio (min): 45 dB
• Input Offset Voltage: 4.5 mV at +/- 5 V
• Supply Current: 16.1 mA at +/- 5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: SOIC-8 Narrow
• Maximum Dual Supply Voltage: +/- 6 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Section
FEEDBACK RESISTOR
The LMH6702 achieves its excellent pulse and distortion
performance by using the current feedback topology. The
loop gain for a current feedback op amp, and hence the
frequency response, is predominantly set by the feedback
resistor value. The LMH6702 is optimized for use with a
237Ω feedback resistor. Using lower values can lead to
excessive ringing in the pulse response while a higher value
will limit the bandwidth. Application Note OA-13 discusses
this in detail along with the occasions where a different R
might be advantageous.
HARMONIC DISTORTION
The LMH6702 has been optimized for exceptionally low
harmonic distortion while driving very demanding resistive or
capacitive loads. Generally, when used as the input amplifier
to very high speed flash ADCs, the distortions introduced by
the converter will dominate over the low LMH6702 distor-
tions shown in the Typical Performance Characteristics sec-
tion. The capacitor C
1 and Figure 2, is critical to achieving the lowest 2
FIGURE 1. Recommended Non-Inverting Gain Circuit
FIGURE 2. Recommended Inverting Gain Circuit
SS
, shown across the supplies in Figure
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nd
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har-
F
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monic distortion. For absolute minimum distortion levels, it is
also advisable to keep the supply decoupling currents
(ground connections to C
Figure 2) separate from the ground connections to sensitive
input circuitry (such as R
Splitting the ground plane in this fashion and separately
routing the high frequency current spikes on the decoupling
caps back to the power supply (similar to "Star Connection"
layout technique) ensures minimum coupling back to the
input circuitry and results in best harmonic distortion re-
sponse (especially 2
If this lay out technique has not been observed on a particu-
lar application board, designer may actually find that supply
decoupling caps could adversely affect HD2 performance by
increasing the coupling phenomenon already mentioned.
Figure 3 below shows actual HD2 data on a board where the
ground plane is "shared" between the supply decoupling
capacitors and the rest of the circuit. Once these capacitors
are removed, the HD2 distortion levels reduce significantly,
especially between 10MHz-20MHz, as shown in Figure 3
below:
At these extremely low distortion levels, the high frequency
behavior of decoupling capacitors themselves could be sig-
nificant. In general, lower value decoupling caps tend to
have higher resonance frequencies making them more ef-
fective for higher frequency regions. A particular application
board which has been laid out correctly with ground returns
"split" to minimize coupling, would benefit the most by having
low value and higher value capacitors paralleled to take
advantage of the effective bandwidth of each and extend low
distortion frequency range.
Another important variable in getting the highest fidelity sig-
nal from the LMH6702 is the package itself. As already
noted, coupling between high frequency current transients
on supply lines and the device input can lead to excess
harmonic distortion. An important source of this coupling is in
fact through the device bonding wires. A smaller package, in
general, will have shorter bonding wires and therefore lower
coupling. This is true in the case of the SOT23-5 compared
to the SOIC package where a marked improvement in HD
can be measured in the SOT23-5 package. Figure 4 below
shows the HD comparing SOT23-5 to SOIC package:
FIGURE 3. Decoupling Current Adverse Effect on a
Board with Shared Ground Plane
nd
order distortion).
G
, R
POS
T
, and R
, and C
IN
NEG
ground connections).
in Figure 1 and
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