LM3544M-L National Semiconductor, LM3544M-L Datasheet - Page 10

• Manufacturer Part Number: LM3544M-L
• Description: IC,Power Control/Management,SOP,16PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LM3544M-L

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

www.national.com
Application Information
tantalum capacitor is recommended. The input supply
should be further bypassed with a 0.01 µF - 0.1 µF ceramic
capacitor, placed close to the device. The ceramic capacitor
reduces ringing on the supply that can occur when a short is
present at the output of a port.
Extending the Fault Flag Delay
While the 7 ms (typical) internal delay in reporting flag
conditions is adequate for most applications, the delay can
be extended by connecting external RC filters to the FLAG
pins, as shown in Figure 5 .
Power Dissipation and Junction Temperature
A few simple calculations will allow a designer to calculate
the approximate operating temperature of the LM3544 for a
given application. The large currents possible through the
low resistance power MOSFET combined with the high
thermal resistance of the SOIC package, in relation to power
packages, make this estimate an important design step.
Begin the estimate by determining R
operating temperature using the graphs in the Typical
FIGURE 5. Typical Circuit for Lengthening the Internal
Flag Delay
FIGURE 6. Self-Powered Hub Connections and Per-Port Voltage Drop
ON
(Continued)
at the expected
10120828
10
Performance Characteristics section of this datasheet. Next,
calculate the power dissipation through the switch with
Equation (1) .
Note: Equation for power dissipation neglects portion that
comes from LM3544 quiescent current because this value
will almost always be insignificant.
Using this figure, determine the junction temperature with
Equation (2) .
Where:
Temperature (˚C).
Compare the calculated temperature with the expected
temperature used to estimate R
match, re-estimate R
temperature and repeat the calculations. Reiterate as
necessary.
PCB Layout Considerations
In order to meet the USB requirements for voltage drop,
droop and EMI, each component used in this circuit must be
evaluated for its contribution to the circuit performance.
These principles are illustrated in Figure 6 . The following
PCB layout rules and guidelines are recommended
1. Place the switch as close to the USB connector as
2. Avoid vias as much as possible. If vias are used, use
3. Place the output capacitor and ferrite beads as close to
4. If ferrite beads are used, use wires with minimum
JA
= SOIC Thermal Resistance: 130˚C/W and T
possible. Keep all V
use at least 50-mil, 1 ounce copper for all V
Solder plating the traces will reduce the trace resistance.
multiple vias in parallel and/or make them as large as
possible.
the USB connector as possible.
resistance and large solder pads to minimize connection
resistance.
T
ON
J
PD = R
= PD
using a more appropriate operating
bus
traces as short as possible and
*
ON
ON
JA
*
. If they do not reasonably
I
+ T
DS
2
A
.
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A
bus
= Ambient
traces.
(1)
(2)