LM3477MM National Semiconductor, LM3477MM Datasheet - Page 21

• Manufacturer Part Number: LM3477MM
• Description: Pulse Width Modulation (PWM) Controller IC
• Manufacturer: National Semiconductor

Specifications of LM3477MM

• Input Voltage Primary Min: 2.95V
• Mounting Type: Surface Mount
• Topology: Buck (Step Down)
• Control Mode: Current
• Duty Cycle Max: 93%
• Input Voltage Primary Max: 35V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Compensation
Choosing C
the power pole and insuring a −20dB/decade slope in the
low frequency magnitude response. In other words, the
phase margin below the crossover frequency will always be
higher than the phase margin at the crossover frequency.
If better transient response times are desired, a second
method is to set f
target crossover frequency. This trades more low frequency
gain for less phase margin, which translates to faster but
more oscillatory step responses. We pick C
47nF).
If the esr zero of the output capacitor (f
more phase margin is required, additional components may
be added to increase the flexibility of the compensator.
Use C
For this example, f
The equations used here for R
mations valid when C
Plotting Open Loop Response earlier in this section. In some
cases, the desired inductance is several times higher than
the optimal inductance set by the internal slope compensa-
tion. This results in a Q lower than 0.15, in which case
additional methods of compensating are presented (see
SAMPLING POLE QUALITY FACTOR section).
Sampling Pole Quality Factor
In a current mode control architecture, there is an inherent
resonace at half the switching frequency. The LM3477/A
internally compensates for this by adding a negative slope to
the PWM control waveform (see DEFAULT/ADJUSTABLE
SLOPE COMPENSATION section). The factor in the power
FIGURE 15. Open Loop Frequency Response for
C2
LM3477 Compensation Design Example
if f
C1
ESR
= 88x10
<
Z2
1
ESR
between f
⁄
2
f
C2
S
−9
= 159 kHz, so use C
, that is if:
<<
F will set f
(Continued)
P1
C
C
C1
and
, C
. For exact equations, see
C1
1
Z2
⁄
2
, and C
decade before f
= f
ESR
P1
) is too low or if
C1
C2
C2
, canceling out
.
= 49nF (use
are approxi-
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C
, the
21
stage equations above, Q, describes how much resonance
will be observed. Q is a function of duty cycle and m
16 shows how the power stage bode plot is affected as Q is
varied from 0.01 to 10. The resonance is caused by two
complex poles at half the switching frequency. If m
low, the resonant peaking could become severe coinciding
with subharmonic oscillations in the inductor current. If m
too high, the two complex poles split and the converter
begins to act like a voltage mode converter and the compen-
sation scheme used above should be changed.
If Q
ing the right half of the imaginary plane (the system is
becoming unstable). In this case, Q must be decreased by
either increasing the inductance, or more preferably, adding
more slope compensation through the R
DEFAULT/ADJUSTABLE SLOPE COMPENSATION sec-
tion).
If Q
creasing in frequency towards the dominant power pole, f
There are three ways to compensate for this. Decrease the
crossover frequency, add a phase lead network, or use the
output capacitor’s ESR to cancel out the low frequency
sampling pole.
One option is to decrease the crossover frequency so that
the phase margin is not as severely decreased by the sam-
pling pole. Decreasing the crossover frequency to between
1kHz to 10kHz is advisable here. As a result, there will be a
decrease in transient response performance.
Another option is the use of the feed-forward capacitor, Cff.
This will provide a positive phase shift (lead) which can be
used to increase phase margin. However, it is important to
note that the effectiveness of Cff decreases with output
voltage. This is due to the fact that the frequencies of the
zero f
is reduced.
The frequency of the feed-forward zero and pole are:
Poles is used to qualify how much resonant peaking is
FIGURE 16. The Quality Factor Q of the Two Complex
>
<
2, the sampling poles are imaginary and are approach-
zff
0.15, it means that one of the sampling poles is de-
and pole f
observed in the Power Stage Bode Plot
pff
get closer together as the output voltage
SL
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resistor (see
www.national.com
c
. Figure
c
is too
c
p1
is
.