HCTL-2001-A00 Avago Technologies US Inc., HCTL-2001-A00 Datasheet - Page 12

• Manufacturer Part Number: HCTL-2001-A00
• Description: IC,Servo Encoder,CMOS,DIP,16PIN,PLASTIC
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2001-A00

• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 16-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Current, Supply: 1 μA
• Function Type: 16-Bits
• Logic Function: Counter/Decoder
• Logic Type: CMOS/LSTLL
• Number Of Circuits: Quad
• Package Type: PDIP-16
• Special Features: Binary, Bus, Schmitt-Trigger, Tri-State
• Temperature, Operating, Range: -40 to +85 °C
• Voltage, Supply: 4.5 to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1880-5; HCTL-2001-A00

12
Cascade Considerations (HCTL-2021-A00/PLC only!)
The HCTL-2021-A00/PLC cascading system allows for
position reads of more than two bytes. These reads
can be accomplished by latching all the bytes and then
reading the bytes sequentially over the 8-bit bus. It is
assumed here that, externally, a counter followed by a
latch is used to count any count that exceeds 16 bits.
This configuration is compatible with the HCTL-2021-
A00/PLC internal counter/latch combination.
Consider the sequence of events for a read cycle that
starts as the HCTL-2021-A00/PLC internal counter rolls
over. On the rising clock edge, count data is updated
in the internal counter, rolling it over. A count-cascade
pulse (CNT
the rising clock edge (t
propagation delays through the external counters and
registers. Meanwhile, with SEL and OE low to start the
read, the internal latches are inhibited at the falling
edge and do not update again till the inhibit is reset.
Figure 12. Decode and Cascade Output Diagram (4x)
CAS
) will be generated with some delay after
CHD
). There will be additional
If the CNT
and this count gets latched a major count error will
occur. The count error is because the external latches
get updated when the internal latch is inhibited.
Valid data can be ensured by latching the external
counter data when the high byte read is started (SEL
and OE low). This latched external byte corresponds
to the count in the inhibited internal latch. The cascade
pulse that occurs during the clock cycle when the read
begins gets counted by the external counter and is
not lost.
For example, suppose the HCTL-2021-A00/PLC count
is at FFFFh and an external counter is at F0h, with the
count going up. A count occurring in the HCTL-2021-
A00/PLC will cause the counter to roll over and a
cascade pulse will be generated. A read starting on
this clock cycle will show FFFFh from the HCTL-2021-
A00/PLC. The external latch should read F0h, but if the
host latches the count after the cascade signal
propagates through, the external latch will read F1h.
CAS
pulse now toggles the external counter