DSPIC30F6010AT-30I/PF Microchip Technology, DSPIC30F6010AT-30I/PF Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F6010AT-30I/PF
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010AT-30I/PF

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F6010A/6015
10. Motor Control PWM – PWM Counter Register
11. I/O Port – Port Pin Multiplexed with IC1
12. I
13. Timer Module
14. PLL Lock Status Bit
DS80258G-page 2
PTMR does not continue counting down after
halting code execution in Debug mode.
The port I/O pin multiplexed with the Input Capture
1 (IC1) function cannot be used as a digital input
pin when the UART auto-baud feature is enabled.
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
Clock switching prevents the device from waking
up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
2
C Module: 10-bit Addressing Mode
2
C module is configured for 10-bit
2
C devices, the A10 and A9 bits may
15. PSV Operations
16. I
17. I
18. I
The following sections describe the errata and work
around to these errata, where they may apply.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
2
2
2
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module
2
2
C module is enabled, the dsPIC
C module is configured as a 10-bit
© 2008 Microchip Technology Inc.
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