DSPIC30F6010-20E/PF Microchip Technology, DSPIC30F6010-20E/PF Datasheet - Page 8
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DSPIC30F6010-20E/PF
Manufacturer Part Number
DSPIC30F6010-20E/PF
Description
IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6010A-30IPF.pdf
(22 pages)
2.DSPIC30F6010-20IPF.pdf
(222 pages)
3.DSPIC30F6010-20IPF.pdf
(30 pages)
4.DSPIC30F4011-20IML.pdf
(236 pages)
Specifications of DSPIC30F6010-20E/PF
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F601020EPF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F6010
EXAMPLE 9:
10. Module: DISI Instruction
11. Module: 32-bit General Purpose Timers
DS80195H-page 8
__T1Interrupt:
When a user executes a DISI #7, for example,
this will disable interrupts for 7 + 1 cycles (7 + the
DISI instruction itself). In this case, the DISI
instruction uses a counter which counts down from
7 to 0. The counter is loaded with 7 at the end of
the DISI instruction.
If the user code executes another DISI on the
instruction cycle where the DISI counter has
become zero, the new DISI count is loaded, but
the DISI state machine does not properly
re-engage and continue to disable interrupts. At
this point, all interrupts are enabled. The next time
the user code executes a DISI instruction, the
feature will act normally and block interrupts.
In summary, it is only when a DISI execution is
coincident with the current DISI count = 0, that the
issue occurs. Executing a DISI instruction before
the DISI counter reaches zero will not produce
this error. In this case, the DISI counter is loaded
with the new value, and interrupts remain disabled
until the counter becomes zero.
Work around
When executing multiple DISI instructions within
the source code, make sure that subsequent DISI
instructions have at least one instruction cycle
between the time that the DISI counter
decrements to zero and the next DISI instruction.
Alternatively, make sure that subsequent DISI
instructions are called before the DISI counter
decrements to zero.
Pairs of 16-bit timers may be combined to form
32-bit timers. For example, Timer2 and Timer3 are
combined into a single 32-bit timer. For this
release of silicon, when a 32-bit timer is prescaled
by ratios other than 1:1, unexpected results may
occur.
Work around
None. The application may only use the 1:1
prescaler for 32-bit timers.
PUSH
.......
BCLR
MOV.B
MOV.B
POP
RETFIE
W0
IFS0, #T1IF
#0xE0, W0
WREG, SR
W0
;Another interrupt occurs
;here and it is processed
;correctly
RAISE IPL BEFORE RETFIE
;Timer1 ISR
12. Module: Output Compare in PWM Mode
13. Module: Output Compare
14. Module: QEI – Reset on Index Pulse
If the desired duty cycle is ‘0’ (OCxRS = 0), the
module will generate a high level glitch of 1 T
The second problem is that on the next cycle after
the glitch, the OC pin does not go high, or, in other
words, it misses the next compare for any value
written on OCxRS.
Work around
There are two possible solutions to this problem:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
• The output compare module is configured and
When these events occur, the output compare
module will drive the pin low for one instruction
cycle (T
Work around
None. However, the user may use a timer interrupt
and write to the associated PORT register to
control the pin manually.
For this release of silicon, the QEI module should
not be operated in the Reset on Index Pulse mode.
Work around
None.
high using the output compare module or a
write to the associated PORT register.
enabled to drive the pin low at some later time
(OCxCON = 0x0002 or OCxCON = 0x0003).
register when operating in PWM mode. In this
case, no 0% duty cycle is achievable.
output compare module can be disabled for
0% duty cycles, and re-enabled for non-zero
percent duty cycles.
CY
) after the module is enabled.
Mode
© 2008 Microchip Technology Inc.
CY
.