DSPIC30F4012-20E/SO Microchip Technology, DSPIC30F4012-20E/SO Datasheet - Page 25
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC30F4012-20E/SO
Manufacturer Part Number
DSPIC30F4012-20E/SO
Description
IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F4012-30ISO.pdf
(238 pages)
3.DSPIC30F4012-30ISO.pdf
(18 pages)
4.DSPIC30F4012-30ISO.pdf
(6 pages)
5.DSPIC30F4012-30ISO.pdf
(16 pages)
6.DSPIC30F4012-30ISO.pdf
(22 pages)
Specifications of DSPIC30F4012-20E/SO
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DSPIC30F401220ESO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4012-20E/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F4012-30ISO PDF datasheet #2
- DSPIC30F4012-30ISO PDF datasheet #3
- DSPIC30F4012-30ISO PDF datasheet #4
- DSPIC30F4012-30ISO PDF datasheet #5
- DSPIC30F4012-30ISO PDF datasheet #6
- Current page: 25 of 238
- Download datasheet (4Mb)
3.0
3.1
The program address space is 4M instruction words. It
is addressable by the 23-bit PC, table instruction
Effective Address (EA) or data space EA, when
program space is mapped into data space as defined
by
incremented by two between successive program
words in order to provide compatibility with data space
addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In
bit 23 allows access to the Device ID, the User ID and
the Configuration bits; otherwise, bit 23 is always clear.
© 2010 Microchip Technology Inc.
Note:
Table
MEMORY ORGANIZATION
Program Address Space
3-1. Note that the program space address is
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
Table
3-1, read/write instructions,
FIGURE 3-1:
dsPIC30F4011/4012
Reset – GOTO Instruction
Reset – Target Address
Alternate Vector Table
Interrupt Vector Table
Device Configuration
Program Memory
(16K instructions)
UNITID (32 instr.)
Data EEPROM
PROGRAM SPACE
MEMORY MAP FOR
dsPIC30F4011/4012
DEVID (2)
User Flash
(Read ‘0’s)
Reserved
Registers
Reserved
Reserved
Reserved
(1 Kbyte)
Reserved
DS70135G-page 25
000000
000002
000004
00007E
000080
000084
0000FE
000100
007FFE
008000
7FFBFE
7FFC00
7FFFFE
800000
8005BE
8005C0
8005FE
800600
F7FFFE
F80000
F8000E
F80010
FEFFFE
FF0000
FFFFFE
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