DSPIC30F3012-20E/ML Microchip Technology, DSPIC30F3012-20E/ML Datasheet - Page 11
![IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F3012-20E/ML
Manufacturer Part Number
DSPIC30F3012-20E/ML
Description
IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(6 pages)
4.DSPIC30F2011-20IP.pdf
(26 pages)
5.DSPIC30F3012-20ISO.pdf
(14 pages)
6.DSPIC30F3012-20ISO.pdf
(20 pages)
Specifications of DSPIC30F3012-20E/ML
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
20. Module: I
© 2008 Microchip Technology Inc.
Note:
When the I
I2CEN bit in the I2CCON register, the dsPIC DSC
device generates a glitch on the SDA and SCL
pins. This glitch falsely indicates “Communication
Start” to all devices on the I
a bus collision in a multi-master configuration.
Additionally, when the I2CEN bit is set, the S and
P bits of the I
‘0’, respectively, which indicate a “Communication
Start” condition.
Work arounds
To avoid this issue, either of the following two work
arounds can be implemented, depending on the
application requirements.
Work around 1:
In a single-master environment, add a delay
between enabling the I
transmission. The delay should be equal to or
greater than the time it takes to transmit two data
bits.
In the multi-master configuration, in addition to the
delay, all other I
nized and wait for the I
before initiating any kind of communication.
Work around 2:
In dsPIC DSC devices in which the I
multiplexed
precedence in the use of the pin, it is possible to
avoid this glitch by enabling the higher priority
module before enabling the I
Use the following procedure to implement this
work around:
1. Enable the higher priority peripheral module
2. Set up and enable the I
Disable the higher priority peripheral module that
was enabled in step 1.
that is multiplexed on the same pins as the I
module.
Work around 2 works only for devices that
share the SDA and SCL pins with another
peripheral that has a higher precedence
over the port latch, such as the UART. The
priority is shown in the pin diagram located
in the data sheet. For example, if the SDA
and SCL pins are shared with the UART
and SPI pins, and the UART has higher
precedence on the port latch pin.
2
2
C
C module is enabled by setting the
2
with
C module are set to values ‘1’ and
2
C masters should be synchro-
other
2
2
C module and the first data
C module to be initialized
2
2
modules
C bus, and can cause
C module.
2
C module.
2
C module is
that
have
2
C
dsPIC30F3012/3013
DS80255F-page 11